參數(shù)資料
型號(hào)： P82C55A
廠商： INTEL CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： CHMOS PROGRAMMABLE PERIPHERAL INTERFACE
中文描述： 24 I/O, PIA-GENERAL PURPOSE, PDIP40
封裝： DIP-40
文件頁(yè)數(shù)： 13/23頁(yè)
文件大?。?/td> 325K
代理商： P82C55A
82C55A
Combinations of MODE 1
Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed
I/O applications.
231256–17
Figure 12. Combinations of MODE 1
Operating Modes
MODE 2 (Strobed Bidirectional Bus I/O).
This
functional configuration provides a means for com-
municating with a peripheral device or structure on a
single 8-bit bus for both transmitting and receiving
data (bidirectional bus I/O). ‘‘Handshaking’’ signals
are provided to maintain proper bus flow discipline in
a similar manner to MODE 1. Interrupt generation
and enable/disable functions are also available.
MODE 2 Basic Functional Definitions:
#
Used in Group A
only
.
#
One 8-bit, bi-directional bus port (Port A) and a 5-
bit control port (Port C).
#
Both inputs and outputs are latched.
#
The 5-bit control port (Port C) is used for control
and status for the 8-bit, bi-directional bus port
(Port A).
Bidirectional Bus I/O Control Signal Definition
INTR (Interrupt Request).
A high on this output can
be used to interrupt the CPU for input or output oper-
ations.
Output Operations
OBF (Output Buffer Full).
The OBF output will go
‘‘low’’ to indicate that the CPU has written data out
to port A.
ACK (Acknowledge).
A ‘‘low’’ on this input enables
the tri-state output buffer of Port A to send out the
data. Otherwise, the output buffer will be in the high
impedance state.
INTE 1 (The INTE Flip-Flop Associated with
OBF).
Controlled by bit set/reset of PC
6
.
Input Operations
STB (Strobe Input).
A ‘‘low’’ on this input loads
data into the input latch.
IBF (Input Buffer Full F/F).
A ‘‘high’’ on this output
indicates that data has been loaded into the input
latch.
INTE 2 (The INTE Flip-Flop Associated with IBF).
Controlled by bit set/reset of PC
4
.
13
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