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參數(shù)資料
| 型號： | P82C55A |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CHMOS PROGRAMMABLE PERIPHERAL INTERFACE |
| 中文描述： | 24 I/O, PIA-GENERAL PURPOSE, PDIP40 |
| 封裝： | DIP-40 |
| 文件頁數(shù)： | 11/23頁 |
| 文件大小： | 325K |
| 代理商： | P82C55A |
82C55A
Input Control Signal Definition
STB (Strobe Input).
data into the input latch.
A ‘‘low’’ on this input loads
IBF (Input Buffer Full F/F)
A ‘‘high’’ on this output indicates that the data has
been loaded into the input latch; in essence, an ac-
knowledgement. IBF is set by STB input being low
and is reset by the rising edge of the RD input.
INTR (Interrupt Request)
A ‘‘high’’ on this output can be used to interrupt the
CPU when an input device is requesting service.
INTR is set by the STB is a ‘‘one’’, IBF is a ‘‘one’’
and INTE is a ‘‘one’’. It is reset by the falling edge of
RD. This procedure allows an input device to re-
quest service from the CPU by simply strobing its
data into the port.
INTE A
Controlled by bit set/reset of PC
4
.
INTE B
Controlled by bit set/reset of PC
2
.
231256–13
Figure 8. MODE 1 Input
231256–14
Figure 9. MODE 1 (Strobed Input)
11
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