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參數(shù)資料
| 型號： | OM6213 |
| 英文描述： | 48 x 84 pixels matrix LCD driver |
| 中文描述： | 48 × 84像素的矩陣LCD驅(qū)動器 |
| 文件頁數(shù)： | 20/40頁 |
| 文件大?。?/td> | 213K |
| 代理商： | OM6213 |
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2001 Nov 07
20
Philips Semiconductors
Product specification
48
×
84 pixels matrix LCD driver
OM6213
Notes to the DC characteristics
1.
The maximum possible V
LCD
voltage that may be generated is dependent on voltage, temperature and (display) load.
2.
Internal clock.
3.
Power-down mode: during Power-down all static currents are switched off.
4.
If external V
LCD
, the display load current is not transmitted to I
DD.
5.
V
LCD
external voltage applied to V
LCDIN
and V
LCDSENSE
inputs; V
LCDOUT
disconnected. V
PR
must be set to 0 to
switch-off the charge pump.
6.
Load current 10
μ
A, outputs tested one at a time.
7.
Valid for values of temperature, V
OP
and TC used at the calibration.
16 AC CHARACTERISTICS
V
DD1
= V
DD2
= 2.5 V to 3.3 V; V
SS
= 0 V; V
LCD
= 4.5 to 9.0 V; T
amb
=
40 to +85
°
C; unless otherwise specified.
Notes
1.
2.
3.
4.
t
frame
= f
clk(ext)
/490.
RES may be LOW before V
DD
goes HIGH (see Fig.16). This is recommended.
Decoupling capacitor V
LCD
/V
SS1
= 100 nF (higher capacitor size increases t
VHRL
or higher V
DD1,2,3
reduces t
VHRL
).
t
H5
is the time from the previous SCLK positive edge (irrespective of the state of SCE) to the negative edge of SCE
(see Fig.15).
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
f
clk(ext)
f
frame
t
VHRL
external clock frequency
frame frequency
reset LOW pulse set-up time
after power-on
reset LOW pulse width
end of reset pulse to interface
being operational
30.9
63
0
34.3
70
37.7
77
30
kHz
Hz
μ
s
internal oscillator; note 1
notes 2 and 3; see Fig.16
t
RW
t
R(op)
see Fig.16
100
1000
ns
ns
Serial bus timing characteristics
f
SCLK
clock frequency
V
DD1
= 3.0 V
±
10%; all signal
timing is based on 20% to 80% of
V
DD
and a maximum rise and fall
time of 10 ns
0
4.00
MHz
T
cy(SCLK)
t
PWH1
t
PWL1
t
S2
t
H2
t
PWH2
t
H5
t
S3
t
H3
t
S4
t
H4
clock cycle time SCLK
SCLK pulse width HIGH
SCLK pulse width LOW
SCE set-up time
SCE hold time
SCE minimum HIGH time
SCE start hold time
D/C set-up time
D/C hold time
SDIN set-up time
SDIN hold time
250
100
100
60
100
100
100
100
100
100
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
note 4
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