參數(shù)資料
型號(hào)： NT7502H-BDT
廠商： Electronic Theatre Controls, Inc.
英文描述： 65 X 132 RAM-Map LCD Controller / Driver
中文描述： 65 × 132 RAM的地圖LCD控制器/驅(qū)動(dòng)器
文件頁(yè)數(shù)： 6/54頁(yè)
文件大?。?/td> 687K
代理商： NT7502H-BDT
NT7502
System Bus Connection Pads
Pad No.
Symbol
I/O
Descriptions
17 - 24
D0 - D7
(SI)
(SCL)
I/O
This is an 8-bit bi-directional data bus that connects to an 8-bit or 16-bit
standard MPU data bus.
When the serial interface is selected (P/S = “L”), then D7 serves as the serial
data input terminal (SI) and D6 serves as the serial clock input terminal (SCL)
At this time, D0 to D5 are set to high impedance.
When the chip select is inactive, D0 to D7 are set to high impedance.
12
A0
I
This is connected to the least significant bit of the normal MPU address bus,
and it determines whether the data bits are data or a command
A0 = “H” indicating that D0 to D7 are display data, and
A0 = “L” indicating that D0 to D7 are control data.
11
RES
I
When RES is set to “L”, the settings are initialized.
The reset operation is performed by the RES signal level.
8, 9
1
CS CS2
I
This is the chip select signal. When
select becomes active, and data/command I/O is enabled.
1
CS = “L” and CS2 = “H”, then the chip
15
RD
(E)
I
When connected to an 8080 MPU, it is active LOW.
This pad is connected to the
RD
signal of the 8080MPU, and the NT7502
data bus is in an output status when this signal is “L”.
When connected to a 6800 Series MPU, this is active HIGH.
This is used as an enable clock input of the 6800 series MPU.
14
WR
W
/
R
(
)
I
When connected to an 8080 MPU, this is active LOW. This terminal connects
to the 8080 MPU
WR
signal. The signals on the data bus are latched at the
rising edge of the
WR
signal.
When connected to a 6800 Series MPU, this is the read/write control signal
input terminal.
When
W
R
/
= “H”: Read
When
W
R
/
= “L”: Write
75
C86
I
This is the MPU interface switch terminal
C86 = “H”: 6800 Series MPU interface
C86 = “L”: 8080 MPU interface
76
P/S
I
This is the parallel data input/serial data input switch terminal
P/S = “H”: Parallel data input
P/S = “L”: Serial data input
The following applies depending on the P/S status:
P/S
"H"
"L"
Data/Command
A0
A0
Data
D0 to D7
SI (D7)
Read/Write
Serial Clock
Write only
SCL (D6)
RDWR
When P/S = “L”, D0 to D5 are HZ. D0 to D5 may be “H”, “L” or Open.
RD
(E) and
WR
(
W
R
/
) are fixed to either “H” or “L”. With serial data input,
RAM display data reading is not supported.
73
CLS
I
Terminal is used to select whether enable or disable the display clock internal
oscillator circuit.
CLS = “H”: Internal oscillator circuit is enabled
CLS = “L”: Internal oscillator circuit is disabled (requires external input).
When CLS = “L”, input the display clock through the CL pad.
6
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
NT7502H-TABF1 制造商:未知廠家 制造商全稱:未知廠家 功能描述:65 X 132 RAM-Map LCD Controller / Driver
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NT751AS12DC12V 制造商:DBLECTRO 制造商全稱:DB Lectro Inc 功能描述:Switching capacity up to 16A.
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