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參數(shù)資料
| 型號： | NT7502H-BDT |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 65 X 132 RAM-Map LCD Controller / Driver |
| 中文描述： | 65 × 132 RAM的地圖LCD控制器/驅動器 |
| 文件頁數(shù)： | 10/54頁 |
| 文件大?。?/td> | 687K |
| 代理商： | NT7502H-BDT |
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NT7502
CS2
SI
SCL
A0
1
CS
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Figure. 1
#
When the chip is not active, the shift registers and the counter are reset to their initial states.
#
Reading is not possible while in serial interface mode.
#
Caution is required on the SCL signal when it comes to line-end reflections and external noise. We recommend the
operation be rechecked on the actual equipment.
Chip Select Inputs
The NT7502 has two chip select pads.
When these pads are set to any other combination, D0 to D7 are high impedance and A0, E and
When serial input interface is selected. the shift register and counter are reset.
1
CS and CS2 can interface to a microprocessor when
1
R
/
CS is low and CS2 is high.
W
inputs are disabled.
Access to Display Data RAM and Internal Registers
The NT7502 can perform a series of pipeline processing between LSI’s using the bus holder of the internal data bus in order to
match the operating frequency of display RAM and internal registers with the microprocessor. For example, the microprocessor
reads data from display RAM in the first read (dummy) cycle, stores it in the bus holder, and outputs it onto system bus in the
next data read cycle.
Also, the microprocessor temporarily stores display data in the bus holder, and stores it in display RAM until the next data write
cycle starts.
When viewed from the microprocessor, the NT7502 access speed greatly depends on the cycle time rather than access time to
the display RAM (t
ACC
). This view shows the data transfer speed to / from the microprocessor can increase. If the cycle time is
inappropriate, the microprocessor can insert the NOP instruction that is equivalent to the wait cycle setup. However, there is a
restriction in the display RAM read sequence. When an address is set, the specified address data is NOT output at the
immediately following read instruction. The address data is output during the second data read. A single dummy read must be
inserted after address setup and after the write cycle (refer to Figure2).
10
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| NT75-1AS12DC12V0.253.5 | 制造商:DBLECTRO 制造商全稱:DB Lectro Inc 功能描述:Low coil consumption. / Switching capacity up to 16A. |
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