參數(shù)資料
型號(hào)： NT7502H-BDT
廠商： Electronic Theatre Controls, Inc.
英文描述： 65 X 132 RAM-Map LCD Controller / Driver
中文描述： 65 × 132 RAM的地圖LCD控制器/驅(qū)動(dòng)器
文件頁(yè)數(shù)： 14/54頁(yè)
文件大?。?/td> 687K
代理商： NT7502H-BDT
NT7502
The Display Data Latch Circuit
The display data latch circuit is a latch that temporarily stores the display data output to the liquid crystal driver circuit from the
display data RAM.
Because the display normal/reverse status, display ON/OFF status, and display all points ON/OFF commands control only the
data within the latch, they do not change the data within the display data RAM itself.
The Oscillator Circuit
This is a CR-type oscillator that produces the display clock. The oscillator circuit is only enabled when M/S = “H” and CLS = “H”.
When CLS = “L” the oscillation stops, and the display clock is input through the CL terminal.
Display Timing Generator Circuit
The display timing generator circuit generates the timing signal to the line address circuit and the display data latch circuit using
the display clock. The display data is latched into the display data latch circuit synchronized with the display clock, and is output
to the data driver output terminal. Reading to the display data liquid crystal driver circuits is completely independent of access to
the display data RAM by the MPU. Consequently, even if the display data RAM is accessed asynchronously during liquid
crystal display, there is absolutely no adverse effect (such as flickering) on the display.
Moreover, the display timing generator circuit generates the common timing and the liquid crystal alternating current signal (FR)
from the display clock. It generates a drive waveform using a 2 frame alternating current drive method, as is shown in Figure 5,
for the liquid crystal drive circuit.
CL
FR
COM0
COM1
RAM
data
SEGn
V
0
V
1
V4
V
SS
V
0
V
1
V4
V
SS
V
0
V
2
V3
V
SS
60
6
65
64
61
62
63
64
65
2
3
4
5
1
2
3
4
5
1
6
Figure. 5
When multiple NT7502 chips are used, the slave chips must be supplied with the display timing signals (FR, CL, DOF) from the
master chip[s].
Table 5 shows the status of the FR, CL, and DOF signals.
Table. 5
Operating Mode
FR
CL
DOF
Master (M/S = “H”)
The internal oscillator circuit is enabled (CLS = “H”)
The internal oscillator circuit is disabled (CLS = “L”)
The internal oscillator circuit is disabled (CLS = “H”)
The internal oscillator circuit is disabled (CLS = “L”)
Output
Output
Input
Input
Output
Input
Input
Input
Output
Output
Input
Input
Slave (M/S = “L”)
14
相關(guān)PDF資料
PDF描述
NT7502H-TABF1 65 X 132 RAM-Map LCD Controller / Driver
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相關(guān)代理商/技術(shù)參數(shù)
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