參數(shù)資料
型號: NT7502H-BDT
廠商: Electronic Theatre Controls, Inc.
英文描述: 65 X 132 RAM-Map LCD Controller / Driver
中文描述: 65 × 132 RAM的地圖LCD控制器/驅(qū)動器
文件頁數(shù): 23/54頁
文件大?。?/td> 687K
代理商: NT7502H-BDT
NT7502
Commands
The NT7502 uses a combination of A0,
RD
(E) and
WR
(
executes each command using internal timing clock only regardless of external clock, its processing speed is very high and its
busy check is usually not required. The 8080 series microprocessor interface enters a read status when a low pulse is input to
the
RD
pad and a write status when a low pulse is input to the
WR
pad. The 6800 series microprocessor interface enters a
read status when a high pulse is input to the
W
/
R
pad and a write status when a low pulse is input to this pad. When a high
pulse is input to the E pad, the command is activated. (For timing, see AC Characteristics.). Accordingly, in the command
explanation and command table,
RD
(E) becomes 1(high) when the 6800 series microprocessor interface reads status of
display data. This is the only different point from the 8080 series microprocessor interface.
Taking the 8080 series microprocessor interface as an example, commands are explained below.
When the serial interface is selected, input data starting from D7 in sequence.
W
R
/
) signals to identify data bus signals. As the chip analyzes and
Command Set
1. Display ON/OFF
Alternatively turns the display on and off.
A0
E
RD
W
R
/
WR
0
D7
D6
D5
D4
D3
D2
D1
D0
Setting
0
1
1
0
1
0
1
1
1
1
Display ON
0
Display OFF
When the display OFF command is executed when in the display all points ON mode, power save mode is entered. See the
section on the power saver for details.
2. Set Display Start Line
Specifies line address (refer to Figure 4) to determine the initial display line, or COM0. The RAM display data becomes the
top line of LCD screen. It is followed by the higher number of lines in ascending order, corresponding to the duty cycle. When
this command changes the line address, smooth scrolling or a page change takes place.
A0
E
RD
W
R
/
WR
0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
A5
A4
A3
A2
A1
A0
%
High-order bit
A5
A4
A3
A2
A1
A0
Line address
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
2
:
:
1
1
1
1
1
0
62
1
1
1
1
1
1
63
23
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