NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.4
08/2009
36
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
dc
Operating, Standby, and Refresh Currents
Parameter
Symbol
Test Condition
Max.
Units
Notes
6K
6KI
75B 75BI
Operating Current
ICC1
1 bank operation
tRC = tRC(min), tCK = min
Active-Precharge command cycling without
burst operation
130
90
mA
1, 2, 3
Precharge Standby Current
in Power Down Mode
ICC2P
CKE ≤ VIL(max), tCK = min,
CS = VIH(min)
4
mA
1
ICC2PS
CKE ≤ VIL(max), tCK = Infinity,
CS = VIH(min)
4
mA
1
Precharge Standby Current
in Non-Power Down Mode
ICC2N
CKE ≥ VIH(min), tCK = min,
CS = VIH (min)
20
mA
1, 5
ICC2NS CKE ≥ VIH(min), tCK = Infinity,
10
mA
1, 7
No Operating Current
(Active state: 4 bank)
ICC3N
CKE ≥ VIH(min), tCK = min,
CS = VIH (min)
35
mA
1, 5
ICC3P
CKE ≤ VIL(max), tCK = min,
5
7
5
7
mA
1, 6
Operating Current (Burst
Mode)
ICC4
tCK = min, Read/ Write command cycling,
Multiple banks active, gapless data, BL = 4
150
110
mA
1, 3, 4
Auto (CBR) Refresh Current
ICC5
tCK = min, tRC = tRC(min)
CBR command cycling
220
200
mA
1
Self Refresh Current
ICC6
CKE ≤ 0.2V
4
mA
1
1. Currents given are valid for a single device. .
2. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of tCK and tRC. Input
signals are changed up to three times during tRC(min).
3. The specified values are obtained with the output open.
4. Input signals are changed once during tCK(min).
5. Input signals are changed once during three clock cycles.
6. Active Standby Current will be higher if Clock Suspend is entered during a burst read cycle (add 1mA per DQ).
7. Input signals are stable.