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參數(shù)資料
| 型號(hào)： | NT5SV8M16FT-75BI |
| 廠商： | NANYA TECHNOLOGY CORP |
| 元件分類： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | 0.400 MM, PLASTIC, TSSOP2-54 |
| 文件頁數(shù)： | 13/65頁 |
| 文件大?。?/td> | 739K |
| 代理商： | NT5SV8M16FT-75BI |
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NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.4
08/2009
20
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The bank undergoing auto-
precharge cannot be reactivated until tDAL, Data-in to Active delay, is satisfied.
Similar to the Read Command, a Write Command with auto-precharge can not be interrupted by a command to the same bank.
It can be interrupted by a Read or Write Command to a different bank, however. The interrupting command will terminate the
write. The bank undergoing auto-precharge can not be reactivated until tDAL is satisfied.
Burst Write with Auto-Precharge
Burst Write with Auto-Precharge Interrupted by Write
DIN A0
COMMAND
NOP
WRITE A
Auto-Precharge
DIN A1
CK
T0
T2
T1
T3
T4
T5
T6
T7
T8
NOP
DIN A0
DIN A1
tCK2, DQs
CAS latency = 2
tCK3, DQs
CAS latency = 3
NOP
*Bank can be reactivated at completion of tDAL.
tDAL
*
(Burst Length = 2, CAS Latency = 2, 3)
See the Clock Frequency and Latency table.
tDAL is a function of clock cycle time and speed sort.
DIN A0
COMMAND
NOP
WRITE A
Auto-Precharge
DIN A1
tDAL
CK
T0
T1
T2
T3
T4
T5
NOP
t
CK3, DQs
CAS latency = 3
WRITE B
DIN B0
DIN B1
DIN B2
DIN B3
T6
T7
T8
NOP
*Bank can be reactivated at completion of tDAL.
*
(Burst Length = 4, CAS Latency = 3)
See the Clock Frequency and Latency table.
tDAL is a function of clock cycle time and speed sort.
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相關(guān)代理商/技術(shù)參數(shù) |
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| NT5SV8M16HS-6K | 制造商:Nanya Technology Corporation 功能描述:DRAM |
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| NT5SV8M8DT-6K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64Mb Synchronous DRAM |
| NT5SV8M8DT-7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64Mb Synchronous DRAM |
| NT5SV8M8DT-7K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64Mb Synchronous DRAM |
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