![](http://datasheet.mmic.net.cn/180000/NT5SV8M16FT-75BI_datasheet_11338977/NT5SV8M16FT-75BI_19.png)
NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.4
08/2009
19
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Although a Read Command with auto-precharge can not be interrupted by a command to the same bank, it can be interrupted
by a Read or Write Command to a different bank. If the command is issued before auto-precharge begins then the precharge
function will begin with the new command. The bank being auto-precharged may be reactivated after the delay tRP.
If interrupting a Read Command with auto-precharge with a Write Command, DQM must be used to avoid DQ contention.
Burst Read with Auto-Precharge Interrupted by Read
Burst Read with Auto-Precharge Interrupted by Write
tRP
COMMAND
NOP
READ A
Auto-Precharge
CK
T0
T2
T1
T3
T4
T5
T6
T7
T8
NOP
tRP
tCK2, DQs
CAS latency = 2
tCK3, DQs
CAS latency = 3
*Bank can be reactivated at completion of tRP.
DOUT A0
DOUT A1
NOP
DOUT A0
DOUT A1
DOUT B0
DOUT B1
READ B
DOUT B2
DOUT B3
DOUT B0
DOUT B1
DOUT B2
DOUT B3
tRP is a function of clock cycle time and speed sort.
See the Clock Frequency and Latency table.
*
(Burst Length = 4, CAS Latency = 2, 3)
COMMAND
NOP
READ A
Auto-Precharge
tRP
CK
T0
T2
T1
T3
T4
T5
T6
T7
T8
NOP
t
CK2, DQs
CAS latency = 2
DQM
NOP
DOUT A0
DIN B0
DIN B1
WRITE B
DIN B2
DIN B3
NOP
DIN B4
*Bank can be reactivated at completion of tRP.
tRP is a function of clock cycle time and speed sort..
See the Clock Frequency and Latency table.
*
(Burst Length = 8, CAS Latency = 2)