參數(shù)資料
型號(hào): NSC800
廠商: National Semiconductor Corporation
英文描述: NSC800TM High-Performance Low-Power CMOS Microprocessor
中文描述: NSC800TM高性能低功耗CMOS微處理器
文件頁(yè)數(shù): 56/76頁(yè)
文件大小: 785K
代理商: NSC800
12.14 Program Control
(Continued)
DJNZ
d
Decrement the B register and conditionally jump to program
location calculated with respect to the program counter and
the displacement d, based on the contents of the B register.
B
w
B
b
1
No flags affected
If B
e
0 continue,
else PC
w
PC
a
d
7
6
5
4
3
2
1
0
0
0
0
1
0
0
0
0
d
b
2
Timing:
If B
i
0
M cycles D 3
T states D 13 (5, 3, 5)
If B
e
0
M cycles D 2
T states D 8 (5, 3)
Addressing Mode:
PC Relative
CALLS
CALL
nn
Unconditional call to subroutine at location nn.
(SP
b
1)
w
PC
H
(SP
b
2)
w
PC
L
SP
w
SP
b
2
PC
w
nn
7
6
5
4
3
2
No flags affected
1
0
1
1
0
0
1
1
0
1
n (low-order byte)
n (high-order byte)
Timing:
M Cycles D 5
T states D 17 (4, 3, 4, 3, 3)
Addressing Mode:
Direct
CALL
cc, nn
Conditional call to subroutine at location nn based on test-
able flag stages.
If cc true,
(SP
b
1)
w
PC
H
(SP
b
2)
w
PC
L
SP
w
SP
b
2
PC
w
nn,
else continue
7
6
5
No flags affected
4
3
2
1
0
1
1
cc
1
0
0
n (low-order byte)
n (high-order byte)
Timing:
If cc true
M cycles D 5
T states 17 (4, 3, 4, 3, 3)
If cc not true
M cycles D 3
T states D 10 (4, 3, 3)
Addressing Mode:
Direct
RETURNS
RET
Unconditional return from subroutine or other return to pro-
gram location pointed to by the top of the stack.
PC
L
w
(SP)
No flags affected
PC
H
w
(SP
a
1)
SP
w
SP
a
2
7
6
5
4
3
2
1
0
1
1
0
0
1
0
0
1
Timing:
M cycles D 3
T states D 10 (4, 3, 3)
Addressing Mode:
Register Indirect
RET
cc
Conditional return from subroutine or other return to pro-
gram location pointed to by the top of the stack.
If cc true,
PC
L
w
(SP)
PC
H
w
(SP
a
1)
SP
w
SP
a
2,
else continue
7
6
5
No flags affected
4
3
2
1
0
1
1
cc
0
0
0
Timing:
If cc true
M cycles D 3
T states D 11 (5, 3, 3)
If cc not true
M cycles D 1
T states D 5
Addressing Mode:
Register Indirect
RETI
Unconditional return from interrupt handling subroutine.
Functionally identical to RET instruction. Unique opcode al-
lows monitoring by external hardware.
PC
L
w
(SP)
No flags affected
PC
H
w
(SP
a
1)
SP
w
SP
a
2
7
6
5
4
3
2
1
0
1
1
1
0
1
1
0
1
0
1
0
0
1
1
0
1
Timing:
M cycles D 4
T states D 14 (4, 4, 3, 3)
Addressing Mode:
Register Indirect
56
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