參數(shù)資料
型號(hào): NSC800
廠(chǎng)商: National Semiconductor Corporation
英文描述: NSC800TM High-Performance Low-Power CMOS Microprocessor
中文描述: NSC800TM高性能低功耗CMOS微處理器
文件頁(yè)數(shù): 22/76頁(yè)
文件大?。?/td> 785K
代理商: NSC800
9.0 Timing and Control
(Continued)
A reset to the CPU will force both IFF
1
and IFF
2
to the reset
state disabling maskable interrupts. They can be enabled by
an EI instruction at any time by the programmer. When an EI
instruction is executed, any pending interrupt requests will
not be accepted until after the instruction following EI has
been executed. This single instruction delay is necessary in
situations where the following instruction is a return instruc-
tion and interrupts must not be allowed until the return has
been completed. The EI instruction sets both IFF
1
and IFF
2
to the enable state. When the CPU accepts an interrupt,
both IFF
1
and IFF
2
are automatically reset, inhibiting further
interrupts until the programmer wishes to issue a new EI
instruction. Note that for all the previous cases, IFF
1
and
IFF
2
are always equal.
The function of IFF
2
is to retain the status of IFF
1
when a
non-maskable interrupt occurs. When a non-maskable inter-
rupt is accepted, IFF
1
is reset to prevent further interrupts
until reenabled by the programmer. Thus, after a non-mask-
able interrupt has been accepted, maskable interrupts are
disabled but the previous state of IFF
1
is saved by IFF
2
TL/C/5171–27
FIGURE 17. Interrupt Mode 2
22
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
NSC800D 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:NSC800TM High-Performance Low-Power CMOS Microprocessor
NSC800D/883C 制造商: 功能描述: 制造商:undefined 功能描述:
NSC800D/B 制造商:Rochester Electronics LLC 功能描述:- Bulk
NSC800D-1I 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:8-Bit Microprocessor
NSC800D-3 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:8-Bit Microprocessor