參數(shù)資料
型號(hào): NSC800
廠(chǎng)商: National Semiconductor Corporation
英文描述: NSC800TM High-Performance Low-Power CMOS Microprocessor
中文描述: NSC800TM高性能低功耗CMOS微處理器
文件頁(yè)數(shù): 49/76頁(yè)
文件大?。?/td> 785K
代理商: NSC800
12.9 Rotate and Shift
(Continued)
7
6
5
4
3
2
1
0
1
1
0
0
1
0
1
1
SRL (HL)
0
0
1
1
1
1
1
0
Timing:
M cycles D 4
T states D 15 (4, 4, 4, 3)
Addressing Mode:
7
6
5
Register Indirect
4
3
2
1
0
SRL (IX
a
d) (for N
X
e
0)
1
1
N
X
1
1
1
0
1
SRL (IY
a
d) (for N
X
e
1)
1
1
0
0
1
0
1
1
d
0
0
1
1
1
1
1
0
Timing:
M cycles D 6
T states D 23 (4, 4, 3, 5, 4, 3)
Addressing Mode:
Indexed
REGISTER/MEMORY
RLD
Rotate digit left and right between the Accumulator and
memory (HL).
TL/C/5171–71
S: Set if result is negative
Z: Set if result is zero
H: Reset
P/V: Set if result parity is even
N: Reset
C: N/A
1
0
7
6
5
4
3
2
1
1
1
0
1
1
0
1
0
1
1
0
1
1
1
1
Timing:
M cycles D 5
T states D 18 (4, 4, 3, 4, 3)
Addressing Mode:
Implied/Register Indirect
RRD
Rotate digit right and left between the Accumulator and
memory (HL).
TL/C/5171–72
S: Set if result is negative
Z: Set if result is zero
H: Reset
P/V: Set if result parity is even
N: Reset
C: N/A
1
0
7
6
5
4
3
2
1
1
1
0
1
1
0
1
0
1
1
0
0
1
1
1
Timing:
M cycles D 5
T states D 18 (4, 4, 3, 4, 3)
Addressing Mode:
Implied/Register Indirect
12.10 Exchanges
REGISTER/REGISTER
EX
DE, HL
Exchange the contents of the 16-bit register pairs DE and
HL.
DE
Y
HL
No flags affected
7
6
5
4
3
2
1
0
1
1
1
0
1
0
1
1
Timing:
M cycles D 1
T states D 4
Addressing Mode:
Register
EX
AF, A’F’
The contents of the Accumulator and flag register are ex-
changed with their corresponding alternate registers, that is
A and F are exchanged with A’ and F’.
A
Y
A’
No flags affected
F
Y
F’
7
6
5
4
3
2
1
0
0
0
0
0
1
0
0
0
Timing:
M cycles D 1
T states D 4
Addressing Mode:
Register
49
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