- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄363666 > NSBMC290VF (National Semiconductor Corporation) Burst Mode Memory Controller PDF資料下載
參數(shù)資料
| 型號： | NSBMC290VF |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Burst Mode Memory Controller |
| 中文描述： | 突發(fā)模式內(nèi)存控制器 |
| 文件頁數(shù)： | 8/20頁 |
| 文件大?。?/td> | 318K |
| 代理商： | NSBMC290VF |
Functional Description
(Continued)
TABLE II. Buffer Control Signals and the Memory Bank for Which they are active
Simple/Pipeline Cycle
Burst Cycle
Signal Name
Read
Write
Read
Write
DBTX
A,B
A,B (Note 1)
DBTXa
A
A (Note 2)
DBTXb
B
B (Note 2)
DBCE
A,B
A,B
A,B (Note 1)
A,B (Note 1)
DBCEa
A
A
A (Note 2)
A, B (Note 1)
DBCEb
B
B
B (Note 2)
A,B (Note 1)
IBTX
A,B
A,B (Note 1)
IBTXa
A
A (Note 2)
IBTXb
B
B (Note 2)
BankB/
*
A (Note 3)
1
e
Memory Bank B is next active, 0
e
Bank A is next
Note 1:
Remains active over the entire burst cycle regardless of the bank being accessed.
Note 2:
Asserted only when the specific bank is being accessed.
Note 3:
Must be externally synchronized to SYSCLK.
The memory buffer strategy required will depend on the
type of DRAMs being used (bit wide vs nibble wide compo-
nents), the access time of these memories, the desired
burst write speed, and the system clock speed. Table III
presents some of the possible configurations with the corre-
sponding mode settings. For a comprehensive discussion of
the selection of a buffer strategy, lease refer to the
NSBMC290 Application Guide. This document expands the
rationale of the selection process and presents specific ap-
plication examples and circuit diagrams.
TABLE III. Possible NSBMC290
Memory/Buffer Configurations
Buffer Type
DRAM
Burst
Write
BMC
Organization
Buffer Mode
74F245
Nibble
2 Cycle
Mode 3
74F245
Bit
2 Cycle
Mode 1
74F245, 74F646
Nibble
1 Cycle
Mode 3
74F245, 74F646
Bit
1 Cycle
Mode 1
Am29C983
Bit
1 Cycle
Mode 2
29827, 29861
Bit
2 Cycle
Mode 0
SYSTEM CLOCK FREQUENCY
The system clock frequency is used to derive the period of
DRAM refresh cycles. The refresh rate is given by (system
clock frequency)/(16 x (programmed value
a
1)). This meets
the nominal refresh requirements for DRAM devices. For
example, if the system clock is 25 MHz and the pro-
grammed value is 24, the NSBMC20 will execute the 256
refresh cycles for a 256k DRAM in 4.096 ms. Bit 13 of the
configuration word in the MSB of the frequency field while
bit 8 is the LSB. The refresh algorithm employed by the
NSBMC290 guarantees the time for complete device re-
fresh, however, the time for individual row refreshes may be
held off to prevent the preemption of a burst.
DRAM SIZE
This two bit field, bit 7 and bit 6, configures the NSBMC290
for the correct memory address size, and hence total mem-
ory block size. Note that the memory in both banks of the
block are required to be of the same size, and organization
in order for correct operation to occur. Table IV lists the
supported device sizes.
TABLE IV. Size Code Settings, DRAM
Density and Address Range Size
Memory
Size Code
(in Bits 7, 6)
DRAM
Memory
Block Size
Address Size
0
64 kB x 1 64 kB x 4
512 KBytes
1
256 kB x 1 256 kB x 4
2 MBytes
2
1 MB x 1 1 MB x 4
8 MBytes
3
4 MB x 1 4 MB x 4
32 MBytes
8
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| NSC800 | NSC800TM High-Performance Low-Power CMOS Microprocessor |
| NSC800D | NSC800TM High-Performance Low-Power CMOS Microprocessor |
| NSC800E | NSC800TM High-Performance Low-Power CMOS Microprocessor |
| NSC800N | NSC800TM High-Performance Low-Power CMOS Microprocessor |
| NSC800V | NSC800TM High-Performance Low-Power CMOS Microprocessor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NSBMC290VF-16 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| NSBMC290VF-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| NSBMC290VF-25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| NSBMC290VF-33 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| NSBMC292 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。