參數(shù)資料
型號(hào)： NSBMC290VF
廠(chǎng)商： National Semiconductor Corporation
英文描述： Burst Mode Memory Controller
中文描述： 突發(fā)模式內(nèi)存控制器
文件頁(yè)數(shù)： 7/20頁(yè)
文件大?。?/td> 318K
代理商： NSBMC290VF
Functional Description
(Continued)
BLOCK ADDRESS
Once configured, a NSBMC290 only responds to addresses
within the block address range configured. The pro-
grammed value corresponds to the starting address of the
block, while the size of the block is determined by the size
of the devices used. For example, if 1M x 1 DRAM devices
are selected, the memory block size is 8M bytes and is al-
ways located on an 8M byte boundary. Figure 1 shows the
least significant bit of the block address for each block size.
BYTE ORDER
When bit 16 of the configuration word is set to 0, the con-
vention used for numbering sequential bytes in a word is
that byte address 0 selects bits 0–7, byte address 1 selects
bits 8–15 and so on. If bit 16 of the configuration word is set
to 1, this ordering is reversed and byte address 0 selects
24–31 etc. The bit order of data within a byte is unaffected
by the byte order selected. This feature facilitates the imple-
mentation of multi-processor systems in which programma-
ble Big/Little Endian byte order is not supported by all proc-
essors.
BURST WRITE CYCLES
The NSBMC290 supports instruction and data reads at a
rate of one access per SYSCLK cycle during bursts. Howev-
er, the flexibility of the data buffer strategy is such that buff-
er and memory device combinations may be selected for
which the data hold time during single clock write cycles
cannot be guaranteed across all system operating condi-
tions of temperature and voltage. A two clock write cycle
has thus been provided in order to support these combina-
tions. Configuration Bit 18 is set to 0 if a two clock data
burst write cycle is required, 1 if single clock write cycle is
possible. The NSBMC290 Application Guide details the fac-
tors that influence the selection of this parameter.
RAS ACCESS CYCLES
To maximize the choice of memory device speeds that may
be used with various system clock rates, the NSBMC290
can be configured such that the Row Address Strobe (RAS)
period lasts for either 3 or 4 clock periods during simple
accesses. When set to 1, configuration bit 17 indicates that
3 clock cycles are to be used, when set to 0, 4 are required.
Calculation of the number of cycles required is detailed in
the NSBMC290 Application Guide.
BUFFER CONTROL MODES
The combination of programmable RAS period and burst
write cycle duration permit the system designer to trade
memory device speed and organization in order to optimize
system performance, cost, and storage capacity. This flexi-
bility is further enhanced by providing multiple methods of
buffering the memory sub-system and the Am29000 Local
Channel.
TABLE I. Interpretation of the Buffer Control
Signals for Various Control Modes
Modes Bits Signal 1
Signal 2
Signal 3 Signal 4
00
01
10
11
DBTxA
DBCeA
DBTx
DBCe
DBTxB
DBCeB
BankB/
*
A
BankB/
*
A
IBTxA
IBTxA
IBTx
IBTx
IBTxB
IBTxB
IBTx
IBTx
Note:
The mode 00 signal names are the defaults used for reference pur-
poses.
The transfer of Instructions and Data from the memory sub-
system to the Local Channel occurs through buffers con-
trolled by the NSBMC290. Of the six signals provided for
this purpose, four operate in multiple modes; the remaining
two (DBLeA, DBLeB) have fixed interpretation. These two
signals provide latch enable controls for transparent latches
for use during data transfers from the Am29000 to memory.
The functions performed by the remaining four signals
change according to the programmed mode. Table I pres-
ents these signals using names that are function derived.
Signals with a DB prefix are used to control Data Bus opera-
tions while those starting with IB control instruction bus op-
erations. Signals containing TX are Buffer transmit controls
which are typically used with buffers that have output en-
ables (transmit relative to the memory system). Buffers such
as 74F245 or 74F646 which have direction and enable pins
are controlled with a CE (chip enable) signal (DBCE,
DBCEa, DBCEb).
Signals ending with A or B are specific to one or the other of
the two interleaved banks of memory controlled by the
NSBMC290; signals without suffixes apply to both banks.
The signal BankB/
*
A, required in some configurations, indi-
cates which DRAM memory bank will be next selected.
7
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