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參數(shù)資料
| 型號： | NSBMC290VF |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Burst Mode Memory Controller |
| 中文描述： | 突發(fā)模式內(nèi)存控制器 |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 318K |
| 代理商： | NSBMC290VF |
Functional Description
PRODUCT OVERVIEW
The NSBMC290 is designed to simplify the interface be-
tween the Am29000 high-speed synchronous channel and
dynamic memories. This integrated circuit responds to all
defined instruction and data access modes of the Am29000,
and handles all required address decoding and multiplexing
for the DRAM memory array. In addition, the NSBMC290
automatically generates refresh cycles to the memory array.
Software configuration is used to setup the memory block
address, refresh rate, byte order, bus buffer control type and
DRAM memory chip size parameters for the NSBMC290. If
two or more memory blocks are used to implement an
Am29000 memory sub-system, the processor can simulta-
neously access one memory block via the data bus and a
second memory block via the instruction bus. If both ac-
cesses are directed to the same memory block, the
NSBMC290 will hold off the second access until the first
has completed; only then will it process the second access.
SYSTEM INTERFACE
The NSBMC290 connects directly to the Am29000 address
bus, instruction and data bus controls signals. The interface
handles simple, pipelined and burst mode access for both
the data and instruction bus, according to the Am29000
channel specification. It requires no external logic to imple-
ment the synchronous channel connection. Thus, it avoids
the propagation delays and signal skews that can detract
from system performance and increase system complexity.
MEMORY INTERFACE
The NSBMC290 directly drives an array of DRAM devices
which can support page mode accesses. The array is orga-
nized as 2 banks of 32 bits each. The supported devices are
all the standard memory size from 64 Kbit to 16 Mbit. Selec-
tion of the device in use is done via software.
During burst accesses, the NSBMC290 executes inter-
leaved page mode accesses to 2 banks. This allows the
memory to run at the full processor speed of 1 memory
cycle
per
processor
cycle.
NSBMC290 controls the memory as four independent of
8-bit bytes in order to allow 8-, 16- and 32-bit accesses.
For
data
accesses,
the
The byte order for interpreting the byte address is software
configurable. However, the NSBMC290 does not detect if
the access overflows a word boundary. The software oper-
ating on the Am29000 should manage the correct alignment
for memory accesses that are not word aligned. Systems
using Am29000 processors whose revision level is previous
to Revision ‘‘C’’ must manage alignment of byte data
through software so that the data will retain correct justifica-
tion.
The NSBMC290 allows for flexibility in the control of instruc-
tion and data buffers for the memory array. Propagation de-
lay is minimized by providing these controls directly, and by
allowing the control strategy to be software programmable.
For example 74F245 or high current Am29861 bus buffers
may be used without external ‘‘glue’’ circuitry.
CONFIGURATION
The NSBMC290 is configured by the first 32-bit memory
read access following deassertion of the
RESET
signal. If
multiple NSBMC290 devices are used in a circuit, they
should be daisy chained together with
RSTOUT
from one
chip connecting to
RESET
of the next chip. When a
NSBMC290 has been configured, it deasserts the
RSTOUT
signal allowing the next NSBMC290 in the chain to then be
configured. All NSBMC290 devices must be configured be-
fore memory accesses are attempted.
TL/V/11803–4
FIGURE 1. NSBMC290 Configuration Word
6
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