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參數(shù)資料
| 型號： | NSBMC290VF |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Burst Mode Memory Controller |
| 中文描述： | 突發(fā)模式內(nèi)存控制器 |
| 文件頁數(shù)： | 12/20頁 |
| 文件大小： | 318K |
| 代理商： | NSBMC290VF |
Typical Application
(Continued)
TL/V/11803–8
FIGURE 4. Burst Read Sequence (Illustrating Burst Suspension)
BURST ACCESS SEQUENCE
When Burst access has been established, the NSBMC290
generates the signal sequence ofFigure 5. This access se-
quence will continue until either canceled or suspended by
the Am29000 or normal burst termination occurs. The
NSBMC290 will preempt the burst sequence only in the
case that a refresh cycle has been requested, and has been
outstanding for a time in excess of 80% of the refresh peri-
od.
FUNCTIONAL OVERVIEW OF BURST ACCESS
Figure 4 diagrams the sequence of events that take place
during a typical burst sequence. This specific example de-
scribes the operations surrounding instruction or data reads.
The example illustrates how burst operation is established,
suspended for a cycle, and subsequently terminated by the
master.
The sequence commences at T
0
when the NSBMC290 is
selected. Once selected, the BMC drives RAS of the memo-
ry bank which contains data for the initial access of the
burst cycle (Bank A in this case). During the next period
(T
1
), CASa is asserted and the RAS for the other memory
bank (RASb) is activated. Access to the second memory
bank is offset by one cycle in order that bank interleave will
occur correctly.
The first word of data is available to the processor by T
3
as
indicated by RDY asserted. Data from the memory must
propagate through any data buffers and meet the setup time
of the 29k processor by T
3
. An extra cycle is inserted into
the start-up phase of the burst sequence if bit 17 of the
configuration register is programed to ‘‘0’’. This increases
the RAS assertion time from 3 cycles to 4 cycles. The re-
sulting delay is inserted during T
2
.
12
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