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參數(shù)資料
| 型號(hào)： | NSBMC290VF |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Burst Mode Memory Controller |
| 中文描述： | 突發(fā)模式內(nèi)存控制器 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大小： | 318K |
| 代理商： | NSBMC290VF |
Pin Descriptions
Am29000 INTERFACE
The following pins have the same function as their counterparts on the Am29000 and are designed to be connected directly to
the Am29000 Synchronous Channel Interface.
Pin
Description
A0-31
Address Bus (Input):
The address bus transfers byte addresses for all accesses to the memory array except in
burst mode. The NSBMC290 can be software configured to any memory block address within the 4 Gbyte
address range.
BINV
Bus Invalid (Input; Active Low):
This input indicates that the address bus and related control signals are invalid.
This signal must be 0 (high) in order for the NSBMC290 to accept any data or instruction requests.
R/
*
W)
READ/
*
WRITE (Input):
This input indicates whether data is being transferred to the data bus (
R/
*
W
high) or to
the memory array (
R/
*
W
low).
DBACK
Data Burst Acknowledge (Output; 3-State, Active Low):
This output signals that burst mode accesses between
the memory array and the data bus can be continued.
DBREQ
Data Burst Request (Input, Active Low):
This input is used to indicate when burst mode access for data is
desired.
DRDY
Data Ready (Output; 3-State, Active Low):
This output is used to signal the completion of a data access cycle.
DREQ
Data Request (Input; Active Low):
This input signal the initiation of a memory access cycle for data.
DREQT0–1
Data Request Type (Input, Active Low):
These inputs specify the address space of the data access. They must
both be 0 (low) in order for the NSBMC290 to accept a data request.
OPT0–2
Data Options (Input; Active Low):
These inputs specify the data transfer size and operating mode. The
NSBMC290 responds only to cycles in which the values 0, 1, 2 are asserted. The use of these signals is
compatible with the specifications for In-Circuit Emulators.
PDA
Pipelined Data Access (Input; Active Low):
This input indicates that the address bus has the address for the
next data access prior to the completion of the present data request.
IBACK
Instruction Burst Acknowledge (Output; 3-State, Active Low):
This output signals that burst mode accesses
between the memory array and the instruction bus can be continued.
IBREQ
Instruction Burst Request (Input; Active Low):
This input is used to request burst mode instruction access.
IRDY
Instruction Ready (Output; 3-state, Active Low):
This output signals are completion of each instruction access.
IREQ
Instruction Request (Input; Active Low):
This input signals the beginning of an instruction access cycle.
IREQT
Instruction Request Type (Input; Active High):
This input specifies the address space of the instruction access.
It must be 0 (low) in order for the NSBMC290 to accept an instruction request.
PIA
Pipelined Instruction Access (input; Active Low):
This input indicates that the address bus has the address for
the next instruction access prior to the completion of the present instruction request.
PEN
Pipeline Enable (Output; 3-State, Active Low):
This output indicates that the NSBMC290 is capable of
accepting the address for the next access before completion of the present access.
RESET
Reset (Input; Active Low):
This input initializes the NSBMC290 to accept the software configuration information.
If more than one NSBMC290 is used for controlling memory, the NSBMC290 chips should be daisy chained with
RSTOUT
from one NSBMC290 chip connecting to
RESET
of the next NSBMC290 Chip.
RSTOUT
Reset Out (Output; Active Low):
This output is active (low) whenever
RESET
is active and remains active until
the NSBMC290 has been software configured.
SYSCLK
System Clock (Input):
This input is used to synchronize the NSBMC290 to the Am29000 local channel interface.
4
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