參數(shù)資料
型號(hào)： NSBMC290VF
廠商： National Semiconductor Corporation
英文描述： Burst Mode Memory Controller
中文描述： 突發(fā)模式內(nèi)存控制器
文件頁(yè)數(shù)： 15/20頁(yè)
文件大?。?/td> 318K
代理商： NSBMC290VF
AC Timing Parameters
(Unless otherwise stated V
CC
e
5.0V
g
5%, 0
§
C
k
T
A
k
70
§
C.)
Y
Symbol
Description
16 MHz
20 MHz
25 MHz
33 MHz
Units
Min
Max
Min
Max
Min
Max
Min
Max
1 t
BSU
2 t
BH
3 t
RQSU
4 t
RQH
5 t
SU
5A t
SU
BlNV Setup
BINV Hold
Request Sync. Setup Time
Request Sync. Hold Time
Synchronous Input Setup
Synchronous Input Setup I/DBREQ only
8
4
7
3
6
3
5
2
ns
ns
ns
ns
ns
ns
17
4
17
9
13
3
13
8
12
3
12
6
10
2
10
4.5
6 t
H
6A t
BRH
7 t
ARA
Synchronous Input Hold
*
SYSCLK to Burst Request Input Hold
Address Input to Row Address output delay
(Note 1)
*
SYSCLK to row address hold
DRAM Row Address Hold (Note 2)
*
SYSCLK to Column Address Valid Delay
(Note 1)
4
4
3
3
3
3
2
2
ns
ns
ns
29
24
22
18
8 t
RAH
8A t
DRAH
9
t
CAV
9
8
7
6
ns
ns
ns
t
CLK
-4
t
CLK
-4
t
CLK
-3
t
CLK
-2
38
32
29
24
10 t
CAH
11 t
RSHL
12 t
RSLH
13 t
CHL
14 t
CLH
15 t
PZH
SYSCLK to Column Address Hold
SYSCLK to RAS Asserted Delay (Note 1)
SYSCLK to RAS De-asserted Delay (Note 1)
SYSCLK to CAS Asserted Delay (Note 1)
SYSCLK to CAS De-asserted (Note 1)
PEN 3-state to Valid Delay Relative to
*
SYSCLK
6
6
5
5
ns
ns
ns
ns
ns
ns
26
23
32
40
30
22
19
27
33
25
20
17
24
30
23
17
14
20
25
19
16 t
PHL
17 t
PLH
18 t
PHZ
PEN Synchronous Assertion Delay
PEN Synchronous Deassertion Delay
PEN Valid to 3-state Delay Relative to
*
SYSCLK
RDY 3-state to Valid Delay Relative to
*
SYSCLK
RDY Synchronous Assertion Delay
RDY Synchronous De-assertion Delay
26
25
29
22
21
24
20
19
22
17
16
18
ns
ns
ns
19 t
RZH
30
25
23
19
ns
20 t
RHL
21 t
RLH
26
25
22
21
20
19
17
16
ns
ns
22 t
RHZ
RDY Valid to 3-state Delay Relative to
*
SYSCLK
Synchronous Latch Enable Assertion delay
Synchronous Latch Enable De-assertion Delay
Synchronous Buffer Enable Assertion Delay
Synchronous Buffer Enable De-assertion Delay
Synchronous R/
*
W Input Setup Time
29
24
22
18
ns
23 t
LEHL
24 t
LELH
25 t
BHL
26 t
BLH
27 t
RWSU
32
42
49
38
27
35
41
32
24
32
37
29
20
26
31
24
ns
ns
ns
ns
ns
8
7
6
5
28 t
RWH
29 t
WEV
Synchronous R/
*
W Input Hold Time
Synchronous Write Enable Valid Delay
Relative to
*
SYSCLK
Synchronous I/DBACK Valid Delay
Synchronous I/DBACK Assertion Delay
Synchronous I/DBACK Deassertion Delay
Synchronous I/DBACK Valid to 3-state Delay
Asynchronous I/DBACK Deassertion delay
relative to I/DREQ
4
3
3
2
ns
ns
59
49
44
37
30 t
BKZH
31 t
BKHL
32 t
BKLH
33 t
BKHZ
34 t
ABKLH
25
29
24
24
22
21
24
20
20
18
19
22
18
18
14
16
18
15
15
12
ns
ns
ns
ns
ns
*
Signal output delays are measured relative to SYSCLK (except as indicated) using a 50 pF load.
Note 1:
Derate the given delays by 0.06 ns per pF of load in excess of 50 pF.
Note 2:
Where t
CLK
e
1/(2
*
Clock Frequency)
15
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