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參數(shù)資料
| 型號： | NHI-1598ET/883 |
| 廠商： | NATIONAL HYBRID INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), MIL-STD-1553 CONTROLLER, CPGA69 |
| 封裝： | 1.100 X 1.100 INCH, CERAMIC, PLUG IN, PGA-69 |
| 文件頁數(shù)： | 78/89頁 |
| 文件大?。?/td> | 569K |
| 代理商： | NHI-1598ET/883 |
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7
3.1.2
Bus Controller Highlights:
Implements all Message Formats and Error Checking
Simple setup and operation. Preset multiple pointer tables and message blocks. Only two Frame
Pointer and Frame Length Registers are required to control unlimited number of message
blocks
BC initialized by writing to three Configuration Registers and the Interrupt Mask Register
Executes lists of messages via Message Frame
Configurable Local Retry and Interrupt Requests Enabled on Message by Message Basis
Configurable Global Retry and Local Retry
Programmable retries per message:
None
Retry Current Bus
Retry Alternate Bus
Retry Alternate Bus then Current Bus.
Programmable response timeout of 14, 18, 26, or 42 microseconds.
Programmable Intermessage Gap Time up to 4 mS with 1 uS resolution.
Extended Intermessage Gap using NO- OP Feature.
Programmable Frame Gap with 64 uS resolution.
Programmable Interrupts for:
End of Message
End of Frame
Response Time Out, Message
Error
Message Retry
RT Status Bit Set
FIFO Overflow.
Non- Maskable Bus Jam Interrupt.
Host controlled commands:
Start BC
Continuous Mode
Stop at End of Message
Stop at End of Frame
Abort,
GOTO Alternate Frame.
Dynamic Bus Switch Upon Successful Retry.
3.1.3
Remote Terminal Highlights:
Dynamic Bus Control Acceptance
DBCA_ L bit is set in configuration register.
Message Illegality is internally programmable. DOES NOT require external PROMS or glue
logic.
Employs data tables with individual tag words which indicate whether or not the data is valid,
updated since last read, in the process of being updated, was received via broadcast
command, or has been lost (i. e. updated more than once by a receive message before being
read).
Optionally sets the subsystem flag bit whenever stale data is transmitted or received data is
overwritten.
Issues interrupts on any subset of T/ R bit, subaddresses, mode commands, broadcast
messages and errors.
Provides interrupt priority input and output pins for daisy- chaining interrupt requests.
messages.
Optionally resets the real- time clock in response to a "Synchronize" mode command.
Optionally updates the lower 16 bits of the real- time clock in response to a "Synchronize
WithData" command.
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