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參數(shù)資料
| 型號： | NHI-1598ET/883 |
| 廠商： | NATIONAL HYBRID INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), MIL-STD-1553 CONTROLLER, CPGA69 |
| 封裝： | 1.100 X 1.100 INCH, CERAMIC, PLUG IN, PGA-69 |
| 文件頁數(shù)： | 77/89頁 |
| 文件大?。?/td> | 569K |
| 代理商： | NHI-1598ET/883 |
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78
11.0.10
TIMING NOTES
The address is latched by the NH- ET on the high- to- low transition of the
*HCS line. TADS, TADH, and TASLC are referenced to the high- to- low
transition of *HCS.
TACK is a function of the contending access performed by the NHi-ET
(see host access table).
The low- to- high transition of HRD_L or I/ O RD_L or HCS_L terminates
the read cycle.
The low- to- high transition of HWRH_L or HWRL_L or I/ O WR_L or HCS_L
terminates the write cycle.
The DTACK_l line is tri- stated after delay TACKH. Its rise time is a function
of the internal 5K ohm pull- up resistor and the external load.
While INTACK_L is low, INTPO_L will be affected by changes in IRQ_L.
ITACK starts after the falling edge of HRD_L and INTACK_L..
11.1.0
TIMING PARAMETER TABLES
11.1.1
HOST READ, WRITE, READ- MODIFY- WRITE TABLE and
SOFTWARE INTERRUPT ACKNOWLEDGE
SYMBOL
PARAMETER
MIN(ns)
Max(ns)
TADS
ADDRESS SETUP TIME
0
-
TADH
ADDRESS HOLD TIME
200
-
THCSCL
HCS_L LOW TO COMMAND LOW
0
-
TACKWH
DATA ACKNOWLEDGE LOW TO WRITE HIGH
0
-
TWASH
HWRH,L_L HIGH TO HCS_L HIGH
0
-
TACKH
END OF CYCLE TO DATA ACKNOWLEDGE HIGH
0
30
TACKL(1)
NO CONTENTION
0
650
TACKL(2)
WITH CONTENTION
0
1500
TACKL(3)
WORST CASE ; ONCE AT START OF MESSAGE
0
3200
TDS
DATA SETUP TIME
0
75
TDH
DATA HOLD TIME
0
-
TACHRH
DATA ACKNOWLEDGE LOW TO READ HIGH
0
-
TRDLZ
HRD_L LOW TO DATA LOW Z
0
20
TRDHDHZ
HRD_L HIGH TO DATA HIGH Z
0
30
TRDHWL
HRD_L HIGH TO WRITE LOW
30
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11.1.2
I/ O READ and TERMINAL ADDRESS READ TABLE
SYMBOL
PARAMETER
MIN(ns)
Max(ns)
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