
-
31
BCST_ MSK/ BCST_ XOR
Bits: 5
BC
This bit determines how the Broadcast bit in the returned status word will be treated.
0 = If the BCST bit in the status word DOES NOT equal bit 4 of ths BC CONTROL WORD, then
the STAT_ SET bit in the BC CONTROL WORD will be set.
1 = If bit 4 of the BC CONTROL WORD is a "0", then the BCST bit in the status word is DON'T
CARE. If bit 4 of the BC CONTROL WORD IS a "1" and the BCST bit in the status word is a
"1", then the STAT_ SET bit in the BC CONTROL WORD will be set.
BUS JAM
Bits: 4: 0
BC
These bits determine the number of excess words that will be accepted from an RT without
declaring that the bus has been jammed by an RT that is transmitting continuously. The range is
from 0 to 31 words. The msb is bit 4. When a BUS_ JAM is detected, the BC issues a non-
maskable interrupt by setting the PLSCMD_ BSJM_ H output pin to a “1”and Halts.
The CPU can cause the BC to continue by writing to one of the bits in CONFIGURATION
REGISTER 2 after taking corrective action (ie: Globally switch all messages to good bus using
Config Reg 1).
4.2.31
MT ADDRESS FILTER (15:0)
Address: 22
R/ W
MT
This register determines which RT addresses, from 0 to 15 will be monitored in the MESSAGE
MONITOR mode.
0 = Accept RT address, store data.
1 = Ignore RT address, NO data stored.
15
14
13
12
11
10
9
8
MASK 15
MASK 14
MASK 13
MASK 12
MASK 11
MASK 10
MASK 09
MASK 08
7
6
5
4
3
2
1
0
MASK 07
MASK 06
MASK 05
MASK 04
MASK 03
MASK 02
MASK 01
MASK 00
4.2.32
MT ADDRESS FILTER (31:16)
Address: 26
R/ W
MT
This register determines which RT addresses, from 16 to 31 will be monitored in the MESSAGE
MONITOR mode.
0 = Accept RT address, store data.
1 = Ignore RT address, NO data stored.
15
14
13
12
11
10
9
8
MASK 31
MASK 30
MASK 29
MASK 28
MASK 27
MASK 26
MASK 25
MASK 24
7
6
5
4
3
2
1
0
MASK 23
MASK 22
MASK 21
MASK 20
MASK 19
MASK 18
MASK 17
MASK 16
4.2.33
BLOCK "A" LAST ADDRESS
Address: 27
R
MT
This register contains the address of the last word in BLOCK "A" for the WORD MONITOR. The
last address is calculated by the protocol chip. It is not necessarily equal to the BLOCK "A" end
address in register 14. This is because any one of up to four words associated with the last in-
coming word in the block could be stored in register 14. In order to keep all the words together,
they are stored contiguously and the last address in BLOCK "A" is stored in this register;
therefore, four addresses must always be reserved after the address in register 14 to
accommodate this situation.