參數(shù)資料
型號(hào)： NHI-1598ET/883
廠商： NATIONAL HYBRID INC
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), MIL-STD-1553 CONTROLLER, CPGA69
封裝： 1.100 X 1.100 INCH, CERAMIC, PLUG IN, PGA-69
文件頁(yè)數(shù)： 10/89頁(yè)
文件大?。?/td> 569K
代理商： NHI-1598ET/883
-
17
4.2.3
BASIC STATUS
Address: 2
R/ W
RT
This register defines the terminal address as well as default values for all status bits. The Status
Word is OR'ed with this register before transmission. The bits in the BASIC STATUS register
correspond to the bits in the STATUS register and their function is defined in MIL- STD- 1553B.
They can be redefined for other protocols.
15
14
13
12
11
10
9
8
TADR4
TADR3
TADR2
TADR1
TADR0
M_ERR
INSTR
SREQ
7
6
5
4
3
2
1
0
RSVD2
RSVD1
RSVD0
BCR
BUSY
SSF
DBCA
TF
The mechanism employed by the protocol chip for initializing the terminal address is designed to
avoid dedicated pins. Upon POR the terminal address and its parity are automatically read from
address 30 on the I/ O bus. The value can be supplied in 2 ways: by enabling the output of an
external terminal address buffer or by employing pull- up/ down resistors to define a default value
for the 6 least significant bits of the I/ O data bus. Odd parity is used to define a valid terminal
address; even parity will inhibit reception on both buses. After POR, the host can change the
terminal address through software by writing to the TADR field with any desired value. In
addition, this operation will enable reception. Providing Bit 2 of Configuration Register is set to
“0”.
The host can check the validity of the parity bit obtained from the I/ O bus by reading address 30;
if the most significant bit in the lower byte equals 1, the parity is invalid.
If the TADR is not defined externally (by pull- down resistors or a buffer), there is no danger of a
false response before host initialization because internal pull- up resistors on the I/ O bus
guarantee an incorrect terminal address parity.
When BUSY= 1, 1553 message accesses to the RAM are inhibited, however the RT will respond
with status as required by MIL- STD- 1553B. The mode commands "Transmit Status Word",
"Transmit Last Command Word", "Reset Remote Terminal", "Transmitter Shutdown", "Override
Transmitter Shutdown" and the reserved mode commands legalized by MIO (see the CONTROL
register for details) are not affected by BUSY. In addition, all output pulses issued after valid
command reception are inhibited when BUSY= 1 (except for the signal MDCDRST which is
pulsed after receiving the mode command "Reset").
After POR( MRST), BUSY is set to "1"; this prevents the RT from using undefined pointers before
the host has had a chance to initialize the POINTER TABLE. The default value for all other
status bits is "0" and the TADR field is loaded with the hardwired address.
The BUSY Bit in the LAST STATUS REGISTER is cleared on receipt of the first command
after a RESET, except if that command is TRANSMIT LAST STATUS or TRANSMIT LAST
COMMAND mode command.
The BUSY Bit in the LAST STATUS REGISTER can be cleared by bit using
BIT 5 in the
RTC CONTROL REGISTER. See RTC CONTROL REGISTER for details.
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