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參數(shù)資料
| 型號： | NHI-1598ET/883 |
| 廠商： | NATIONAL HYBRID INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), MIL-STD-1553 CONTROLLER, CPGA69 |
| 封裝： | 1.100 X 1.100 INCH, CERAMIC, PLUG IN, PGA-69 |
| 文件頁數(shù)： | 51/89頁 |
| 文件大?。?/td> | 569K |
| 代理商： | NHI-1598ET/883 |
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54
COMMAND WITHOUT DATA WORD
No response
Bits set:
BROADCAST WITH EXTRA DATA WORD
No response
Bits set:
INV & BCST to "1" in TW
BROADCAST WITHOUT DATA WORD
No response
Bits set:
6.0.0
INITIALIZATION
There are several types of initialization that can set up the NHi- ET parameters.
6.1.0
INTERNAL INITIALIZATION
There are two methods of initializing the NHi ET. Each will produce the same results. They are:
Hardware( MRST) and Software (writing to address 15, data not used). After these resets have
been performed, the NHi ET is set to the RT mode and all internal state machines are reset.
The hardwire terminal address is loaded when a hardware or software reset occurs. The hardwire
address is connected to I/ O DAT( 5: 0) pins. I/ O DAT( 4: 0) are used for the address and I/ O
DAT5 is used to set odd parity in the address. The address is wired using external 4.7K pull-
down resistors to set a low and internal 64K pull- up resistors to set a high.
The following table summarizes the condition of internal registers after a reset has been
performed.
Note: All register bit set to 0 at reset except as noted.
REGISTER RESET TABLE
ADDR
REGISTER
BITS=1
COMMENTS
0
CONTROL
HWD
1
POINTER TABLE ADDRESS
LOADED WITH 4096 DEC WORD
2
BASIC STATUS*
HARDWIRE ADDRESS LOADED
21
CONFIGURATION 3
3
INTERRUPT MASK
ALL
ALL INTERRUPTS ARE MASKED
4
INTERRUPT VECTOR
3
INTERRUPT REQUEST
4
AUXILLIARY VECTOR
UNDEFINED
5,6
RTC; HIGH.LOW
NOT AFFECTED BY RESET
7
RTC CONTROL
8
FIFO
RESET ONLY BY MRST
11
LAST COMMAND
UNDEFINED
12
LAST STATUS*
HARDWARE ADDRESS LOADED
18
ENCODER STATUS
19
CONDITION
9,11-13
13
FRAME “A” POINTER
LOADED WITH 2058 DEC
16
FRAME “B”POINTER
LOADED WITH 4096 DEC
14
FRAME "A" LENGTH
CLEARED
17
FRAME "B" LENGTH
CLEARED
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