參數(shù)資料
型號: NDC652
廠商: Fairchild Semiconductor Corporation
英文描述: P-Channel Logic Level Enhancement Mode Field Effect Transistor
中文描述: P溝道增強(qiáng)模式的邏輯電平場效應(yīng)晶體管
文件頁數(shù): 3/10頁
文件大小: 247K
代理商: NDC652
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DRAIN-SOURCE DIODE CHARACTERISTICS
I
S
V
SD
Continuous Source Diode Current
-1.3
A
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= -1.3 A
(Note 2)
-0.8
-1.2
V
Notes:
1. R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
θ
JC
is guaranteed by
design while R
θ
CA
is determined by the user's board design.
P
D
(
t
) =
T
J
T
A
R
θ
J A
(
t
)
=
T
J
T
A
R
θ
J C
+
R
θ
CA
(
t
)
=
I
D
2
(
t
R
DS
(
ON
)
T
J
Typical R
θ
JA
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 78
o
C/W when mounted on a 1 in
2
pad of 2oz cpper.
b. 125
o
C/W when mounted on a 0.01 in
2
pad of 2oz cpper.
c. 156
o
C/W when mounted on a 0.003 in
2
pad of 2oz cpper.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300μs, Duty Cycle < 2.0%.
NDC652P Rev. D1
1a
1b
1c
相關(guān)PDF資料
PDF描述
NDC652P P-Channel Logic Level Enhancement Mode Field Effect Transistor
NDC7001 Dual N & P-Channel Enhancement Mode Field Effect Transistor
NDC7001C Dual N & P-Channel Enhancement Mode Field Effect Transistor
NDC7002 Dual N-Channel Enhancement Mode Field Effect Transistor
NDC7002N Dual N-Channel Enhancement Mode Field Effect Transistor
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參數(shù)描述
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NDC7001 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Dual N & P-Channel Enhancement Mode Field Effect Transistor
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