參數(shù)資料
型號(hào)： NAND256W4A2AZA6E
廠商： NUMONYX
元件分類： PROM
英文描述： 16M X 16 FLASH 3V PROM, 12000 ns, PBGA55
封裝： 8 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, VFBGA-55
文件頁(yè)數(shù)： 5/58頁(yè)
文件大小： 1406K
代理商： NAND256W4A2AZA6E
NAND128-A, NAND256-A
Memory array organization
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2
Memory array organization
The memory array comprises NAND structures where 16 cells are connected in series.
The memory array is organized in blocks where each block contains 32 pages. The array is
split into two areas, the main area and the spare area. The main area of the array stores
data, whereas the spare area is typically used to store error correction codes, software flags
or bad block identification.
In x8 devices the pages are split into a main area with two half pages of 256 bytes each and
a spare area of 16 bytes. In the x16 devices the pages are split into a 256-word main area
and an 8-word spare area. Refer to Figure 7: Memory array organization.
2.1
Bad blocks
The NAND flash 528-byte/264-word page devices may contain bad blocks, that is blocks
that contain one or more invalid bits whose reliability is not guaranteed. Additional bad
blocks may develop during the lifetime of the device.
The bad block information is written prior to shipping (refer to Section 2.1: Bad blocks for
more details).
Table 4 shows the minimum number of valid blocks in each device. The values shown
include both the bad blocks that are present when the device is shipped and the bad blocks
that could develop later on.
These blocks need to be managed using bad blocks management, block replacement or
error correction codes (refer to Section 7: Software algorithms).
Table 4.
Valid blocks
Density of device
Minimum
Maximum
256 Mbits
2008
2048
128 Mbits
1004
1024
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