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參數(shù)資料
| 型號： | NAND256W4A2AZA6E |
| 廠商： | NUMONYX |
| 元件分類： | PROM |
| 英文描述： | 16M X 16 FLASH 3V PROM, 12000 ns, PBGA55 |
| 封裝： | 8 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, VFBGA-55 |
| 文件頁數(shù)： | 20/58頁 |
| 文件大?。?/td> | 1406K |
| 代理商： | NAND256W4A2AZA6E |
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NAND128-A, NAND256-A
Device operations
27/58
6.4
Copy back program
The copy back program operation copies the data stored in one page and reprogram it in
another page.
The copy back program operation does not require external memory and so the operation is
faster and more efficient because the reading and loading cycles are not required. The
operation is particularly useful when a portion of a block is updated and the rest of the block
needs to be copied to the newly assigned block.
If the copy back program operation fails an error is signalled in the status register. However,
as the standard external ECC cannot be used with the copy back operation bit error due to
charge loss cannot be detected. For this reason it is recommended to limit the number of
copy back operations on the same data and or to improve the performance of the ECC.
The copy back program operation requires the following three steps:
1.
The source page must be read using the Read A command (one bus write cycle to
setup the command and then 4 bus write cycles to input the source page address).
This operation copies all 264 words/ 528 bytes from the page into the page buffer.
2.
When the device returns to the ready state (Ready/Busy High), the second bus write
cycle of the command is given with the 4 bus cycles to input the target page address.
Refer to Table 10 for the addresses that must be the same for the source and target
pages.
3.
Then the confirm command is issued to start the P/E/R controller.
After a copy back program operation, a partial-page program is not allowed in the target
page until the block has been erased. See Figure 15 for an example of the copy back
operation.
Figure 15.
Copy back operation
Table 10.
Copy back program addresses
Density
Same address for source and target pages
128 Mbits
A23
256 Mbits
A24
I/O
RB
Source
Address Inputs
SR0
ai07590b
8Ah
70h
00h
Copy Back
Code
Read
Code
Read Status Register
Target
Address Inputs
tBLBH1
(Read Busy time)
10h
Busy
tBLBH2
(Program Busy time)
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參數(shù)描述 |
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| NAND32GAH0HZA5E | 制造商:Micron Technology Inc 功能描述:NAND EMMC - Trays |
| NAND32GAH0HZA5F | 制造商:Micron Technology Inc 功能描述:NAND EMMC - Tape and Reel |
| NAND32GAH0PZA5E | 制造商:Micron Technology Inc 功能描述:EMMC 4.3 4GB 12X16 41NM - Trays |
| NAND32GAH0PZA5F | 制造商:Micron Technology Inc 功能描述:NAND EMMC - Tape and Reel |
| NAND32GAHAKZO6E | 制造商:Micron Technology Inc 功能描述:AUTOMOTIVE - Trays |
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