參數(shù)資料
型號(hào)： NAND256W4A2AZA6E
廠商： NUMONYX
元件分類： PROM
英文描述： 16M X 16 FLASH 3V PROM, 12000 ns, PBGA55
封裝： 8 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, VFBGA-55
文件頁數(shù)： 36/58頁
文件大小： 1406K
代理商： NAND256W4A2AZA6E
NAND128-A, NAND256-A
DC and AC parameters
41/58
Table 20.
AC characteristics for operations(1)
Symbol
Alt.
symbol
Parameter
3 V devices Unit
tALLRL1
tAR
Address Latch Low to
Read Enable Low
Read electronic signature
Min
10
ns
tALLRL2
Read cycle
Min
10
ns
tBHRL
tRR
Ready/Busy High to Read Enable Low
Min
20
ns
tBLBH1
Ready/Busy Low to
Ready/Busy High
Read busy time, 128-Mbit, 256-Mbit,
dual die
Max
12
s
tBLBH2
tPROG
Program busy time
Max
500
s
tBLBH3
tBERS
Erase busy time
Max
3
ms
tBLBH4
Reset busy time, during ready
Max
5
s
tWHBH1
tRST
Write Enable High to
Ready/Busy High
Reset busy time, during read
Max
5
s
Reset busy time, during program
Max
10
s
Reset busy time, during erase
Max
500
s
tCLLRL
tCLR
Command Latch Low to Read Enable Low
Min
10
ns
tDZRL
tIR
Data Hi-Z to Read Enable Low
Min
0
ns
tEHQZ
tCHZ
Chip Enable High to Output Hi-Z
Max
20
ns
tELQV
tCEA
Chip Enable Low to Output Valid
Max
45
ns
tRHRL
tREH
Read Enable High to
Read Enable Low
Read Enable High hold time
Min
15
ns
tRHQZ
tRHZ
Read Enable High to Output Hi-Z
Max
30
ns
TEHQX
TOH
Chip Enable High or Read Enable High to Output Hold
Min
10
ns
TRHQX
tRLRH
tRP
Read Enable Low to Read
Enable High
Read Enable pulse width
Min
25
ns
tRLRL
tRC
Read Enable Low to Read
Enable Low
Read cycle time
Min
50
ns
tRLQV
tREA
Read Enable Low to
Output Valid
Read Enable access time
Max
35
ns
Read ES access time(1)
tWHBH
tR
Write Enable High to
Ready/Busy High
Read busy time, 128-Mbit, 256-Mbit
dual die
Max
12
s
tWHBL
tWB
Write Enable High to Ready/Busy Low
Max
100
ns
tWHRL
tWHR
Write Enable High to Read Enable Low
Min
60
ns
tWLWL
tWC
Write Enable Low to Write
Enable Low
Write cycle time
Min
50
ns
1.
ES = electronic signature.
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