參數(shù)資料
型號(hào): NAND04GW3C2AN6F
廠商: NUMONYX
元件分類: PROM
英文描述: 512M X 8 FLASH 3V PROM, 45 ns, PDSO48
封裝: 12 X 20 MM, LEAD FREE, PLASTIC, TSOP-48
文件頁(yè)數(shù): 18/51頁(yè)
文件大?。?/td> 500K
代理商: NAND04GW3C2AN6F
NAND04GA3C2A, NAND04GW3C2A
6 Device operations
6.10.2
P/E/R Controller and Cache Ready/Busy Bit (SR6)
Status Register bit SR6 has two different functions depending on the current operation.
During Cache Read operations SR6 acts as a Cache Ready/Busy bit, which indicates
whether the Cache Register is ready to accept new data. When SR6 is set to '0', the Cache
Register is busy and when SR6 is set to '1', the Cache Register is ready to accept new data.
During all other operations SR6 acts as a P/E/R Controller bit, which indicates whether the
P/E/R Controller is active or inactive. When the P/E/R Controller bit is set to ‘0’, the P/E/R
Controller is active (device is busy); when the bit is set to ‘1’, the P/E/R Controller is inactive
(device is ready).
6.10.3
P/E/R Controller Bit (SR5)
The Program/Erase/Read Controller bit indicates whether the P/E/R Controller is active or
inactive. When the P/E/R Controller bit is set to ‘0’, the P/E/R Controller is active; when the
bit is set to ‘1’, the P/E/R Controller is inactive.
6.10.4
Error Bit (SR0)
The Error bit is used to identify if any errors have been detected by the P/E/R Controller. The
Error Bit is set to ’1’ when a program or erase operation has failed to write the correct data to
the memory. If the Error Bit is set to ‘0’ the operation has completed successfully.
6.10.5
SR4, SR3, SR2 and SR1 are Reserved
相關(guān)PDF資料
PDF描述
NAND512R3A2CN6E 512 Mbit, 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
NAND512R3A2CN6F 512 Mbit, 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
NAND512R3A2C 512 Mbit, 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
NAND512R4A2CN6F 512 Mbit, 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
NAND512R4A2CZA6E 512 Mbit, 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
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