參數(shù)資料
型號： NAND04GW3C2AN6F
廠商： NUMONYX
元件分類： PROM
英文描述： 512M X 8 FLASH 3V PROM, 45 ns, PDSO48
封裝： 12 X 20 MM, LEAD FREE, PLASTIC, TSOP-48
文件頁數(shù)： 16/51頁
文件大?。?/td> 500K
代理商： NAND04GW3C2AN6F
NAND04GA3C2A, NAND04GW3C2A
6 Device operations
Figure 9.
Random Data Input During Sequential Data Input
6.8
Block Erase
Erase operations are done one block at a time. An erase operation sets all of the bits in the
addressed block to ‘1’. All previous data in the block is lost.
An erase operation consists of three steps (refer to Figure 10:
1.
One bus cycle is required to setup the Block Erase command. Only addresses A19 to
A30 are used, the other address inputs are ignored.
2.
Three bus cycles are then required to load the address of the block to be erased. Refer
to Table 7 for the block addresses of each device.
3.
One bus cycle is required to issue the Block Erase confirm command to start the P/E/R
Controller.
The operation is initiated on the rising edge of write Enable, W, after the confirm command
is issued. The P/E/R Controller handles Block Erase and implements the verify process.
During the Block Erase operation, only the Read Status Register and Reset commands will
be accepted, all other commands will be ignored.
Once the program operation has completed the P/E/R Controller bit SR6 is set to ‘1’ and the
Ready/Busy signal goes High. If the operation completed successfully, the Write Status Bit
SR0 is ‘0’, otherwise it is set to ‘1’.
I/O
Address
Inputs
ai08664
Data Intput
80h
Cmd
Code
Address
Inputs
Data Input
85h
5 Add cycles
Main Area
Spare
Area
Col Add 1,2
Row Add 1,2,3
Cmd
Code
2 Add cycles
Main Area
Spare
Area
Col Add 1,2
RB
Busy
tBLBH2
(Program Busy time)
SR0
10h
70h
Confirm
Code
Read Status Register
相關(guān)PDF資料
PDF描述
NAND512R3A2CN6E 512 Mbit, 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
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NAND512R3A2C 512 Mbit, 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
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