參數(shù)資料
型號(hào)： MX98905B
廠商： Electronic Theatre Controls, Inc.
英文描述： The MX98905 is designed for easy implementation of CSMA/CD local area networks,
中文描述： 該MX98905是專為易于實(shí)現(xiàn)的多址/光盤局域網(wǎng)，
文件頁數(shù)： 40/86頁
文件大?。?/td> 352K
代理商： MX98905B
40
P/N: PM0365
REV. 1.3, NOV 20 ,1995
MX98905B
3. CONFIGURATION REGISTERS
3.1 CONFIGURATION REGISTER A (R/W) (CA)
This register can be accessed by reading 0AH of
internal page 0 register followed by writing to that
address. If other Read/Write takes place between the
read and the write, then write to 0AH will access the
Remote Byte Count Register 0.
IOAD0
IODA1
IOAD2
INT0
INT1
INT2
FREAD
MEMIO
0
1
2
3
4
5
6
7
Bits
SYMBOL
BIT
DESCRIPTION
IOAD2-0
D0-D2
I/O ADDRESS.
These three bits determine the base I/O address of the MX98905
controller when enhanced mode is disabled (NPGEN of HCMR is low). When the
enhanced mode is enabled, the base I/O address will be determined by 5 bits, which
are IOAD2-0 of CA, NPGEN and PGSEL of HCMR. See I/O base determination for
details.
INT2-0
D3-D5
INTERRUPT LINE USED.
Two interrupt modes are supported by the MX98905,
which can be enabled by setting INTMOD of Configuration C.
Direct Drive Mode : In this mode, an interupt output pin will be driven active on a valid
interrupt condition (see ISR for more detail). Only one pin is driven in this mode
depending on the following condition, the other three will remain TRI-STATE.
INT2
X
X
X
X
INT1
0
0
1
1
INT0
0
1
0
1
INTERUPT
INT0
INT1
INT2
INT3
Code Output Mode : INT3 is the active interrupt output while pins INT0-INT2 are
programmable outputs reflecting the values on bits 3 to 5, i.e., when bits 3 and 4 of
CA is high, then INT0, INT1 and INT3 are driven.
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