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參數(shù)資料
| 型號： | MX98905B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | The MX98905 is designed for easy implementation of CSMA/CD local area networks, |
| 中文描述： | 該MX98905是專為易于實現(xiàn)的多址/光盤局域網(wǎng)， |
| 文件頁數(shù)： | 4/86頁 |
| 文件大小： | 352K |
| 代理商： | MX98905B |
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4
P/N: PM0365
REV. 1.3, NOV 20 ,1995
MX98905B
PIN DESCRIPTIONS
A. ISA BUS INTERFACE
SYMBOL
PIN TYPE
PIN NUMBER
DESCRIPTION
SA0-SA19
I
94-97, 99-106,
108-115
LATCHED ADDRESS BUS: Low-order bits of the system's 24-bit
address bus. These lines are enabled onto the bus when BALE is
high and latched when BALE is deasserted. The MX98905 uses
these bits to decode the boot PROM address and internal registers.
In shared memory mode, they are used to decode accesses to
memory of the MX98905.
LA17-LA23
I
76-82
UNLATCHED ADDRESS BUS: High-order 7 bits of the 24-bit system
address bus. These lines are valid on the falling edge of BALE. The
MX98905 uses these bits to decode shared memory address in
shared memory mode. The validity of M16L depends on these
signals only.
SD0-SD15
I/O
127, 128, 130,
131, 133, 134,
SYSTEM DATA BUS: 16-bit system data bus. Used to transfer data
between the system and the MX98905.
136, 137, 73, 72
70, 69, 67,
66, 64, 63
BALE
I
88
BUS ADDRESS LATCH ENABLE: Active-high signal. Used to latch
valid addresses from the current Bus Master on the falling edge of
BALE.
SBHEL
I
83
SYSTEM BUS HIGH ENABLE: Active-low. Indicates that the system
expects a transfer on the address on the bus is 16 bits wide.
IO16L
O
84
16-BIT I/O TRANSFER: Active-low. In I/O mode this signal indicates
that the MX98905 is responding to a 16-bit I/O access by driving 16
bits of data on SD0-SD15.
M16L
O
86
16-BIT MEMORY TRANSFER: Active-low.
MWRL
I
74
MEMORY WRITE STROBE: Active-low. System uses this signal to
write to the memory map of the MX98905.
MRDL
I
75
MEMORY READ STROBE: Active-low. System uses this signal to
read from the memory map of the MX98905.
SMRDL,
SMWRL
I
119, 120
LOW MEMORY STROBES: Active-low. The MX98905 uses MRDL
and MWRL in 16-bit memory mode and will use SMRDL and SMRL in
memory mode when ATXT is low (8-bit mode). Note that SMRDL and
SMWRL are also used to access the BOOT PROM.
IOWRL
I
118
I/O WRITE STROBE: Active-low. Strobe from system to write to the
I/O Map of the MX98905.
IORDL
I
117
I/O READ STROBE: Active-low. Strobe from system to read from the
I/O Map of the MX98905.
相關PDF資料 |
PDF描述 |
|---|---|
| MX98905B | IEEE 802.3, 10BASE5, 10BASE2 Controller and Integrated Bus Interface(IEEE 802.3, 10BASE5, 10BASE2控制器和集成總線接口) |
| MX98905BFC | The MX98905 is designed for easy implementation of CSMA/CD local area networks, |
| MXA2312A | Low Cost, +2,-2 g Dual Axis Accelerometer with Analog Outputs |
| MXA2500K | Ultra Low Cost, 【1.0 g Dual Axis Accelerometer with Absolute Outputs |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MX98905BFC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:The MX98905 is designed for easy implementation of CSMA/CD local area networks, |
| MX98L715BEC | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:3.3V SINGLE CHIP FAST ETHERNET NIC CONTROLLER |
| MX-9C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MX |
| MX-9G | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MX |
| MX9G100B | 制造商:Panasonic Industrial Company 功能描述:90x90 gearhead for 40W motor,100:1 |
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