參數(shù)資料
型號: MX98905B
廠商: Electronic Theatre Controls, Inc.
英文描述: The MX98905 is designed for easy implementation of CSMA/CD local area networks,
中文描述: 該MX98905是專為易于實現(xiàn)的多址/光盤局域網(wǎng),
文件頁數(shù): 28/86頁
文件大?。?/td> 352K
代理商: MX98905B
28
P/N: PM0365
REV. 1.3, NOV 20 ,1995
MX98905B
24. COLLISION RECOVERY
If transmission has collided with another station, the
buffer management logic, which monitors the transmit
circuitry will reset the FIFO and restore the Transmit
DMA pointers for retransmission of the packet. When
collision is detected, the COL bit in TSR will be set and
the NCR (Number of Collisions Register) will be
incremented. If each of the 15 retransmissions results
in a collision, the transmission will be terminated and
the ABT bit in the TSR will be set. If excessive
collisions (i.e., 16 consecutive collisions) are
encountered, NCR reads as zeros and transmission is
aborted.
25. TRANSMIT PACKET ASSEMBLY FORMAT
The following diagrams show the format for assem-
bling packets before they are transmitted for different
byte- ordering schemes. The various formats are
selected in the Data Configuration Register.
DA = Destination Address
SA = Source Address
T/L = Type/Length Field
DA1
DA3
DA5
SA1
SA3
SA5
T/T1
DATA1
DA0
DA2
DA4
SA0
SA2
SA6
T/L0
DATA0
BIT D15
D8 D7
D0
BOS = 0, WTS -1 in Data Configuration Register. This
format used with Series 32000, 808X-type processors.
DA0
DA2
DA4
SA0
SA2
SA4
T/L0
DATA0
DA1
DA3
DA5
SA1
SA3
SA5
T/L1
DATA1
BIT D15
D8 D7
D0
BOS = 1, WTS = 1 in Data Configuration Register. This
format is used with 68000-type processors.
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