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參數資料
| 型號： | MX98905B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | The MX98905 is designed for easy implementation of CSMA/CD local area networks, |
| 中文描述： | 該MX98905是專為易于實現的多址/光盤局域網， |
| 文件頁數： | 32/86頁 |
| 文件大?。?/td> | 352K |
| 代理商： | MX98905B |
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32
P/N: PM0365
REV. 1.3, NOV 20 ,1995
MX98905B
27. DIRECT MEMORY ACCESS CONTROL (DMA)
The DMA capabilities of the ENC greatly simplify use
of the MX98905 in typical configuration. The local
DMA channel transfers data between FIFO, which is
inside the ENC, and memory which is outside the ENC.
There are two kinds of local DMA type: Local DMA
Read and Local DMA Write. Local DMA Read moves
data from memory into FIFO on transmission. Should
a collision occur (up to 15 times), the packet is
retransmitted with no processor intervention. Local
DMA Write transfers data from FIFO to memory on
reception.
A remote DMA channel is also provided on the ENC to
accomplish transfers between a buffer memory and a
system memory whenever the I/O map board design is
required. The two DMA channels (local DMA and
remote DMA) can alternatively be combined to form a
single 32-bit address with 8- or 16-bit data.
28. DUAL DMA CONFIGURATION
Network activity is isolated on a local bus, where the
ENC's local DMA channel performs burst transfers
between the buffer ring and the ENC's FIFO. The
remote DMA transfers data between the buffer ring
and the host memory by means of a bi-directional I/O
port. Meanwhile, remote DMA provides local
addressing capability and is used as a slave DMA by
the host. Host side addressing must be provided by a
host DMA or the CPU. The ENC allows Local and
Remote DMA operations to be interleaved because
the ENC takes care of the bus arbitration problem
itself.
29. INTERNAL REGISTERS
All internal registers are mapped into three pages and
selected by two bits, PS1 and PS0, of Command
Register. Input pins RA0-RA3 are used to address
these internal registers which are 8-bit wide and are
commonly accessed during ENC register read/write
operation. For user's convenience, registers that are
commonly accessed during ENC operation are
mapped into page 0. Page 1 registers are used
primarily for initialization while Page 2 registers are
used for diagnostics. Partitioned registers make one
write/read cycle possible for accessing those
commonly used registers.
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PDF描述 |
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| MX98905B | IEEE 802.3, 10BASE5, 10BASE2 Controller and Integrated Bus Interface(IEEE 802.3, 10BASE5, 10BASE2控制器和集成總線接口) |
| MX98905BFC | The MX98905 is designed for easy implementation of CSMA/CD local area networks, |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MX98905BFC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:The MX98905 is designed for easy implementation of CSMA/CD local area networks, |
| MX98L715BEC | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:3.3V SINGLE CHIP FAST ETHERNET NIC CONTROLLER |
| MX-9C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MX |
| MX-9G | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MX |
| MX9G100B | 制造商:Panasonic Industrial Company 功能描述:90x90 gearhead for 40W motor,100:1 |
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