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參數(shù)資料
| 型號： | MX10F202FC |
| 廠商： | MACRONIX INTERNATIONAL CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 4/47頁 |
| 文件大?。?/td> | 253K |
| 代理商： | MX10F202FC |
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12
P/N:PM0762
REV. 1.0, MAY. 22, 2003
MX10F202FC
Specifications subject to change without notice, contact your sales representatives for the most update information.
Interrupt system
The MX10F202FC contains a 8-source 4 external interrupts, Timer 0, Timer1, watch timer and UART structures
with two priority levels.
Each External interrupts INT0, INT1, INT2, and INT3 can be either level-activated or transition-activated depending
on bits IT0 and IT1 in TCON SFR and IT2, IT3 in INTCON SFR. The flags that actually generate these interrupts
are bits IE0, IE1 in TCON and IE2,IE3 in INTCON. When an external interrupt is generated, the corresponding
request flag is cleared by the hardware when the service routine is vectored to, if the interrupt is transition-
activated. If the interrupt is level-activated the external source has to hold the request active until the requested
interrupt is actually generated. Then it has to deactive the request before the interrupt service routine is completed,
otherwise another interrupt will be generated.
The Timer 0 and Timer 1 Interrupts are generated by TF0 and TF1, which are set by a rollover in their respective
Timer/counter register (except for Timer 0 in Mode 3 of the serial interface). When a Timer interrupt is generated,
the flag that generated it is cleared by the on-chip hardware when the service routine is vectored to.
IE : INTERRUPT ENABLE REGISTER
This register is located at address A8H.
Table. 9 IE SFR (A8H)
765432
10
EA
EX3
EX2
ES
ET1
EX1
ET0
EX0
(MSB)
(LSB)
keep the above table with the following table
Table. 10 Description of IE bits
MNEMONIC POSITION
FUNCTION
EA
IE.7
Disable all interrupt
- Low, all disabled.
- High, each interrupt source is individually enabled or disabled by setting or
clearing its enable bit.
EX3
IE.6
Enable / Disable External interrupt 3.
- Low, disabled
- High, enabled
EX2
IE.5
Enable / Disable External Interrupt 2.
- Low, disabled
- High, enabled
ES
IE.4
Enable / Disable UART interrupt.
- Low, disabled
- High, enabled
ET1
IE.3
Enable / Disable Timer1 overflow interrupt.
EX1
IE.2
Enable / Disable External interrupt 1.
- Low, disabled
- High, enabled
ET0
IE.1
Enable / disable Timer0 overflow interrupt.
EX0
IE.0
Enable / Disable External interrupt 0.
- Low, disabled
- High, enabled
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