參數(shù)資料
型號(hào)： MX10F202FC
廠商： MACRONIX INTERNATIONAL CO LTD
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PQFP100
封裝： PLASTIC, QFP-100
文件頁(yè)數(shù)： 21/47頁(yè)
文件大?。?/td> 253K
代理商： MX10F202FC
28
P/N:PM0762
REV. 1.0, MAY. 22, 2003
MX10F202FC
Specifications subject to change without notice, contact your sales representatives for the most update information.
Pulse Width Modulated Outputs
The MX10F202FC contains two pulse width modulated output channels (see Figure. 15). These channels generate
pulses of programmable length and interval. The repetition frequency is defined by an 8-bit prescaler PWMP, which
supplies the clock for the counter. The prescaler and counter are common to both PWM channels. The 8-bit counter
counts modulo 255, i.e., from 0 to 254 inclusive. The value of the 8-bit counter is compared to the contents of two
registers: PWM0 and PWM1. Provided the contents of either of these registers is greater than the counter value,
the corresponding PWM0 or PWM1 output is set LOW. If the contents of these registers are equal to, or less than
the counter value, the output will be HIGH. The pulse-width-ratio is therefore defined by the contents of the
registers PWM0 and PWM1. The pulse-width-ratio is in the range of 0 to 1 and may be programmed in increments
of 1/255.
Buffered PWM outputs may be used to drive DC motors. The rotation speed of the motor would be proportional to
the contents of PWMn. The PWM outputs may also be configured as a dual DAC. In this application, the PWM
outputs must be integrated using conventional operational amplifier circuitry. If the resulting output voltages have
to be accurate, external buffers with their own analog supply should be used to buffer the PWM outputs before
they are integrated. The repetition frequency f
PWM, at the PWMn outputs is give by :
f
PWM
=
f
OSC
2 x (1 + PWMP) x 255
This gives a repetition frequency range of 123Hz to 31.4KHz (f
OSC = 16MHz). At fOSC = 24MHz, the frequency range
is 184Hz to 47.1KHz. By loading the PWM registers with either 00H or FFH, the PWM channels will output a
constant HIGH or LOW level, respectively. Since the 8-bit counter counts modulo 255, it can never actually reach
the value of the PWM registers when they are loaded with FFH.
When a compare register (PWM0 or PWM1) is loaded with a new value, the associated output is updated
immediately. It does not have to wait until the end of the current counter period. Both PWMn output pins are driven
by push-pull drivers. These pins are not used for any other purpose.
The PWM function is enabled by setting SPR EBTCON bit 2,3. After reset, SFR EBTCON bit 2,3 need to be set to
use P1.4 or P1.5 as the PWM output, otherwise P1.4& P1.5 are general I/O ports.
Prescaler frequency control register PWMP
Reset Value = 00H
PWMP (FEH)
76543
210
MSB
LSB
PWMP.0-7
Prescaler dividsion factor = PWMP +1.
Reading PWMP gives the current reload value. The actual count of the prescaler cannot be read.
Reset Value = 00H
PWM0 (FCH)
76543210
PWM1 (FDH)
MSB
LSB
PWM0/1.0-7} Low/high ratio of PWMn =
(PWMn)
255 - ( PWMn)
EBTCON SFR (EBH)
7654
3
2
1
0
----
PWM1E
PWM0E /EW
-
PWM1E : Selection of P1.4 function as either PWM output or a port line, After reset PWM1E bit is low, and P1.4
is a normal port line.
PWM0E : Selection of P1.5 function as either PWM output or a port line, After reset PWM0E bit is low, and P1.5
is a normal port line.
/EW : After reset, /EW bit is set, and WDT is disable.
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