
24
P/N:PM0762
REV. 1.0, MAY. 22, 2003
MX10F202FC
Specifications subject to change without notice, contact your sales representatives for the most update information.
Power saving modes : active power control, idle, sleep and power down modes
In order to enable lowest power consumption in system application, MX10F202FC has user friendly power control
mechanism as follows :
1) Active power control : used to turn off un-used peripherals in specific applications. For instance, UART might
not be used in audio CD application, then programmer can disable it to save power.
2) Idle mode : used to turn off 80C51 during certain conditions.
3) Sleep mode : used to turn off the whole system except LCD and possibly watch Timer.
4) Power down mode : turn off the whole system.
PCON : Power Control Register (PCON)
PCON SFR (87H)
765
4
3
2
1
0
SMOD -
SCEER WLE
CF1
CF0 PD
IDC
SMOD : Doubl band rate bit for UART.
SLEEP : Sleep mode bit. Setting it activates sleep mode, and could be terminated as the way to terminate the pull
down mode.
WLE : Watch dog load enable. This flag must be set prior to loading WDT and is cleaned when WDT is loaded.
CF1/CF0 : general-prepose flag bit.
PD : Power - down bit. Setting it activates power - down mode.
IDL : idle mode bit. Setting it activates idle mode.
Active power control mode
PCON1 : POWER CONTROL REGISTER 2
Table. 23 PCON1 SFR (F1H)
765
4
3
2
1
0
-
TD
UARTD WDTD PWMD
1
WTD
LCDD
Table. 24 Description of PCON1 bits
. TD : Timer0/1 Disable bit. Setting it to shut-down Timer0/1.
. UARTD: UART Disable bit. Setting it to shut-down UART.
. WDTD : WatchDog Timer Disable bit. Setting it to shut-down WDT.
. PWMD : Pulse Width Modulation Disable bit. Setting it to shut-down PWM.
. WTD : Watch Timer Disable bit, Setting it to shu-down W T.
. BIT 2 must write "1"
. LCDD : LCD Disable bit. Setting it to shut-down all LCD relative modules.