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參數(shù)資料
| 型號(hào)： | MX10F202FC |
| 廠商： | MACRONIX INTERNATIONAL CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 20/47頁 |
| 文件大?。?/td> | 253K |
| 代理商： | MX10F202FC |
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27
P/N:PM0762
REV. 1.0, MAY. 22, 2003
MX10F202FC
Specifications subject to change without notice, contact your sales representatives for the most update information.
Watchdog Timer
The Watchdog Timer (WDT) see Fig.14 , consists of an 11-bit prescaler and an 8-bit Timer formed by SFR T3. The
Timer is incremented every 1.5 ms, derived from the system clock frequency of 16 MHz by the following formula :
f
Timer = fclk / (12 x (2048)). The 8-bit Timer increments every 12 x 2048 cycles of the on-chip oscillator. When a Timer
overflow occurs, the microcontroller is reset. The internal RESET signal is not inhibited when the external RST pin
is kept 0 into high impedance, no matter if the XTAL-clock is running or not.
To prevent a system reset the Timer must be reloaded in time by the application software. If the processor suffers
a hardware / software malfunction, the software will fail to reload the Timer. This failure will result in an overflow
thus prevent the processor from running out of control. This time interval is determined by the 8-bit reload value
that is written into register T3.
Watchdog time interval = [T3] x 12 x 2048 / oscillator frequency
The watch-dog Timer can only be reloaded if the condition flag WLE (SFR PCON bit 4) has been previously set
high by software. At the moment the counter is loaded WLE is automatically cleared.
In the idle state the watchdog Timer and reset circuitry remain active.
The watchdog Timer is controlled by the watchdog enable signal EW (SFR EBTCON bit 1). A LOW level enables
the watchdog Timer. A HIGH level disable the watchdog Timer.
Fig. 14 Watchdog Timer T3
Internal Bus
to reset circuitry
Timer T3
(8-bit)
LOAD LOADEN
Internal Bus
WLE
PD
LOADEN
Prescaler
(11-bit)
Clear
fCLK/12
Write T3
EW
PCON. 4
PCON. 1
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