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參數(shù)資料
| 型號： | MV6001 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | HDLC/DMA CONTROLLER |
| 中文描述： | 的HDLC / DMA控制器 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大小： | 239K |
| 代理商： | MV6001 |
MV6001
5
D7
X
X
X
X
X
X
X
0
0
1
1
Condition
Currently transmitting data
Transmitter disabled, transmission COMPLETE (status read after an interrupt)
Transmitter disabled, transmission ABORTED (status read after an interrupt)
Receiver enabled, free to receive
Currently receiving data
Receiving IDLE
Receiving FLAGS
Receiver disabled, ABORTED frame received (status read after an interrupt)
Receiver disabled, OVERRUN frame received (status read after an interrupt)
Receiver disabled, TOO LONG frame received (status read after an interrupt)
Receiver disabled, VALID frame received (status read after an interrupt)
D1
0
0
1
X
X
X
X
X
X
X
X
D2
X
X
X
1
X
X
X
0
0
0
0
D3
X
X
X
X
0
1
0
X
X
X
X
D4
X
X
X
X
0
0
1
X
X
X
X
D5
X
X
X
X
X
X
X
1
0
0
0
D6
X
X
X
X
X
X
X
0
1
0
1
Status Register
D0
1
0
0
X
X
X
X
X
X
X
X
Figure 6: Status interrupt
Regisler
Function
TFL
Transmitter Frame Length LS Byte
Transmitter Frame Length MS Byte
TA
Transmitter Address LS Byte
Transmitter Address MS Byte
S
Status
C
Control
RFL
Receiver Frame Length LS Byte
Receiver Frame Length MS Byte
RMFL
Receiver Maximum Frame Length LS Byte
Receiver Maximum Frame Length MS Byte
RA
Receiver Address LS Byte
Receiver Address MS Byte
Length
(Bits)
8
3
8
8
8
8
8
3
8
3
8
8
A3
0
0
0
0
1
1
1
1
1
1
1
1
A2
0
0
1
1
0
0
0
0
1
1
1
1
A1
1
1
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
1
1
0
1
0
1
0
1
R/W
R/W
R/W
R/W
R/W
R
W
R
R
R/W
R/W
R/W
R/W
Address
(Hex)
2
3
6
7
9
9
A
B
C
D
E
F
Figure 7: Register addresses
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MV6001B0DG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:HDLC/DMA CONTROLLER |
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| MV6001BODG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| MV6001BODP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| MV601 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:REMOTE CONTROL RECEIVER |
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