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參數(shù)資料
| 型號(hào)： | MV6001 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | HDLC/DMA CONTROLLER |
| 中文描述： | 的HDLC / DMA控制器 |
| 文件頁(yè)數(shù)： | 5/12頁(yè) |
| 文件大小： | 239K |
| 代理商： | MV6001 |
MV6001
4
CONTROL
The receiver has two control bits in the control register,
receive enable (D3) and receive reset (D4). Once the RA and
RMFL registers have been loaded, the receive enable bit can
be set at any time to allow the receiver to receive a frame.
Once set, the receive enable bit cannot be overwritten and
receive reset is disabled until a frame has been received.
Receiver reset will reset the
R
lNT
interrupt bit, registers
RFL, RMFL, RA and bits D2 - D7 of the status register.
INTERRUPT
A receive interrupt (
R
INT
) is generated whenever a frame is
received. The status register can then be read to check the
status of the received frame. The interrupt is reset by writing a
receiver reset to the control register. Since the reset will clear
the receiver bits in the status register, the register must be read
before writing the reset to the control register.
STATUS
The receiver uses bits D2 - D7 of the status register (see
Figs. 5 and 6). A valid frame is indicated by both ‘overrun’ (D6)
and ‘frame too long’ (D7) bits being high. Following R
INT
the
‘free to receive’ bit (D2) should be low, indicating that a frame
has been received. The abort, overrun and long frame bits will
be set according to the state of the frame received. The flag
(D4) and idle (D3) bits monitor the incoming signal
continuously even when the receiver is disabled.
FRAME LENGTH REGISTER
Having received a frame and read the status reqister, the
received frame length can be read from the RFL register. The
frame length is given as an eleven bit number and includes the
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
RECEIVED
FRAME
TOO LONG
RECEIVED
OVERRUN
FRAME
RECEIVED
ABORT
RECEIVING
FLAGS
RECEIVING
IDLE
FREE TO
RECEIVE
TRANS-
MISSION
ABORTED
TRANS-
MITTING
DATA
RECEIVE BITS
TRANSMIT BITS
Figure 5: Status register
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
LOOPBACK
ENABLE
DON'T
CARE
DON'T
CARE
RECEIVE
RESET
RECEIVE
ENABLE
TRANSMIT
RESET
TRANSMIT
ABORT
TRANSMIT
ENABLE
Figure 4: Control register
2 FCS bytes in the count. The reqister should be read before a
receiver reset.
LOOPBACK
Bit D7 of the control register, the loopback bit is provided
for testing purposes. When the bit is set high an internal
connection is made between the transmitter output and
receiver input. The main transmitter output (TX
OP
) transmits
IDLE (transmitted data is always available on T
OP2
). The
receiver is clocked from TCK. The loopback bit will respond to
every write to the control register.
DIRECT MEMORY ACCESS (FIG.11)
All data transfers to or from memory are carried out by the
DMA controller. Each time it receives a request from the
transmitter or receiver it will carry out one DMA cycle, i.e. only
one byte is transferred at a time. Clashes between transmitter
and receiver are resolved in favour of the receiver, otherwise
operation is on a first come, first served basis.
REGISTERS
Fig.7 shows the addresses for the various instruction and
status registers. All registers are readable from and writable to
except for S, C and RFL. The S and C registers have the same
address, which one is accessed is determined by whether a
read (status) or write (control) operation is carried out.
Transmitter registers should not be written to when
transmitting (except to ABORT a frame), likewise receiver
registers should not be written to when receiving. The TA and
RA registers update continuously during transmission and
reception respectively, giving the next address to be read from
or written to.
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