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參數(shù)資料
| 型號(hào)： | MV6001 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | HDLC/DMA CONTROLLER |
| 中文描述： | 的HDLC / DMA控制器 |
| 文件頁(yè)數(shù)： | 3/12頁(yè) |
| 文件大?。?/td> | 239K |
| 代理商： | MV6001 |
MV6001
2
PIN DESCRIPTION
Pin No.
Name
I/O
Function
1,10,20
GND
0V supply
. All 3 pins must be connected.
2 - 9
A
0
- A
7
I/O
Address Bus
. Output for memory A
0
- A
7
addressing. Input for register
addresses A
0
- A
3
.
Test Enable
. Tie to GND for normal operation.
11
TST
I
12-19
A
8
/D
0
- A
15
/D
7
TOP2
I/O
Data Bus/High Order Address
. Multiplexed data and address bus.
21
O
Transmitter Out
. Alternative output to TX
OP
. This output is not affected by
loop back (see Operating Notes - LOOPBACK).
22
T
INT
O
Transmitter Interrupt
. An interrupt is generated whenever transmission
of a frame is ended, either following the last FCS byte of a complete frame of when
an abort sequence is transmitted. The interrupt is reset by the control
register.
23
R
INT
O
Receiver Interrupt
. An interrupt is generated whenever a frame is received.
The interrupt is reset by the counter register.
24
ASB
O
Address Strobe
. Strobes the Address High byte from the
Data/Address Bus into an external latch.
25
AEN
O
Address Enable
. Enables the external address latch.
26
RX
IP
RCK
I
Receiver Input
. Serial HDLC data input, clocked in by RCK.
27
I
Receiver Data Clock
. Provides clock to the receiver section, frequency
should be at the required data rate, this need not necessarily the the same as the
transmit data rate.
28
TCK
I
Transmitter Data Clock
. This input provides a clock signal for the
transmitter section and should be set to the desired transmit data rate.
29
TX
OP
MODE
O
Transmitter output.
Main transmitter output for serial data.
30
I
Bus Control Mode Select
. Controls the polarity of BAK and BRQ.
MODE = V
CC
gives active LOW, MODE = GND gives active HIGH.
Write Register.
Loads data from data bus into register addressed by A
0
- A
3
.
Read Register
. Reads addressed register onto data bus
31
WR
I
32
RD
I
33
DMACK
I
DMA Clock.
This input provides clock to the DMA section. The DMA clock rate
should be at least ten times the sum of the transmit and receive data rates.
34
CS
I
Chip Select
. Enables
RD
and
WR
inputs.
35
BAK
I
Bus Acknowledge
. Input from processor relinquishing control of bus. See
pin 30, Bus Mode Select.
36
BRQ
O
Bus Request
. Output to processor requesting the bus for a DMA cycle. See pin
30, Bus Mode Select.
37
MR
I
Master Reset
. Resets everything.
38
MWR
O
Memory Write
. This is a three-state output to write data into memory during
DMA cycles.
39
MRD
O
Memory Read
. 3-state output to read data from memory during DMA cycles.
40
V
CC
±
5V
±
10% supply.
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