參數(shù)資料
型號: MV6001
廠商: Zarlink Semiconductor Inc.
英文描述: HDLC/DMA CONTROLLER
中文描述: 的HDLC / DMA控制器
文件頁數(shù): 2/12頁
文件大?。?/td> 239K
代理商: MV6001
MV6001
1
DS3138-2.1
MV6001
HDLC/DMA CONTROLLER
The MV6001 is a combined HDLC transceiver and DMA
controller capable of providing serial communications at rates
up to 128K bits/second, and handling direct memory access
clock rates up to 8MHz.
FEATURES
I
Data Rates up to 128K Bits/s
I
DMA Rate up to 8MHz
I
Low Power CMOS
I
Simple Interfacing to Popular 8-Bit Processors
I
Frame Length up to 2K Bytes
I
Low Host-Processor Overhead
I
Conforms to ECMA40 and Related Standards
(CCITT X25, X75, 1.440, ISO3309, ANSI X3.66,
FED-STD 1003, FIPS71)
APPLICATIONS
I
ISDN Terminals
I
LANs
I
X25 p.s.s. Networks
ORDERING INFORMATION
MV6001 B0 DP
(Commercial Plastic DIP)
MV6001 B0 DG
(Commercial Ceramic DIP)
GND
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
GND
TST
A
8
/D
0
A
9
/D
1
A
10
/D
2
A
11
/D
3
A
12
/D
4
A
13
/D
5
A
14
/D
6
A
15
/D
7
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
CC
MRD
MWR
MR
BRQ
BAK
CS
DMACK
RD
WR
MODE
TX
OP
T
CK
R
CK
RX
IP
AEN
ASB
R
INT
T
INT
T
OP2
MV6001
DP40
DG40
Figure 1: Pin connections - top view
OP T
OP2
T
INT
TCK
TX
DMA
RX
REGISTERS
ADDRESS
BUS
ADDRESS/
DATA
BUS
R
INT
RCK
RX
IP
BRQ
MRD
CS
MODE
MWR
BAK
TST
MR
RD
WR
A0, A7
A8/D0, A15/D7
TFL
TA
S
C
RFL
RMFL
RA
Figure 2: Block diagram
ADVANCE INFORMATION
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