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MV6001
3
01111110
FLAG
ADDRESS
1 OR N* BYTES
CONTROL
1 OR 2 BYTES
DATA
FRAME CHECK SEQUENCE
2 BYTES
01111110
FLAG
FINISH
START
USER FIELDS
≤
2047 BYTES
MV6001 GENERATED
*N is any integer
Figure 3
Fig.3 shows the construction of an HDLC frame. The start
and finish of the frame are determined by FLAGS (the binary
pattern 01111110). To prevent spurious recognition of flags in
the user fields, the transmitter automatically inserts a ‘0’ after
five successive ‘1 ‘s. The inserted ‘0’s are removed by the
receiver, and hence are not seen by the user. Each HDLC
frame contains a 2 byte frame check sequence produced by a
cyclic redundancy generator in the transmitter. This sequence
is checked by the receiver to validate the frame.
There are two other sequences which have specific
meanings - IDLE and ABORT. The IDLE state is the
transmission of at least 15 continuous ‘1’s without inserted
zeros. ABORT is 7 to 14 consecutive ‘1’s without inserted
zeros sandwiched between two zeros.
FUNCTIONAL DESCRIPTION
The MV6001 consists of four main sections; transmitter,
receiver, DMA unit and register bank. Each of the transminer~
receiver and DMA unit have their own clocks running at the
required data rates. There are no restrictions on the relative
timing between transmit and receive clocks, the DMA clock
rate should be greater than ten times the sum of the transmit
and receive clock rates.
TRANSMISSION
In its steady state the transmitter produces a continuous
stream of FLAGS until the control register is loaded with a
transmit instruction. The transmitter then, at intervals, requests
the DMA unit to fetch a byte of data. This is then transferred
from the system memory via the data bus to the transmitter. (If
the DMA unit should fail to fetch a byte of data by the time the
next request arrives then an under-run will occur and the
transmitter will transmit an ABORT sequence). Data is
converted into a serial stream with inserted zeros after five
ones, and the 16-bit frame check sequence is appended at the
end of each frame. As soon as the last bit of the FCS has been
clocked out, the TINT OUtPUt goes low to inform the
processor that transmission has ended.
INITIALISATION
To start transmission, two items of information are required
- the start address for the data to be transmitted, and the length
of the user fields are loaded into the TA and TFL registers
respectively, after which the transmit enable bit (D0) can be set
at any time to start transmission. Once a transmission has
been started, the only way it can by stopped is to set the abort
bit (D1). The transmitter will then transmit the abort sequence
followed by flags. Transmitter reset (D2) resets the transmitter
interrupt TINT, clears the TA and TFL registers and bits D0
and D1 of the status register. Transmitter reset is disabled
during a transmission.
INTERRUPT
A transmitter interrupt (
T
INT
) is generated whenever a
transmission ceases, the status register can then be read to
check if the frame was aborted or not. The interrupt is reset by
writing a transmitter reset to the control register. NB. The
status register must be read before a transmitter reset as this
will alter the contents of the status register.
STATUS
The transmitter has two status bits - transmitting data (Do)
and abort (D1) The transmitting data bit should always be low
after T
INT
signifying that transmission is ended. The abort bit
will be high whenever a frame is aborted either by an abort
instruction to the control register, or internally due to an under-
run .
RECEPTION
The receiver accepts serlal data, removes inserted zeros
and checks the frame check sequence. For each byte of data
received, the receiver section generates a DMA request to
transfer the data to memory. If the DMA controller fails to make
the transfer before the next request from the receiver, then the
receiver will drop out and give a receiver. interrupt with the
code in the status register for overrun. If the number of bytes
received reaches the number in the receive maximum frame
length registerthe receiverwilldropoutand give an interrupt with
the code in the status register for frame too long.
INITIALISATION
The RA register (2 bytes) is loaded with the address where
the first received byte of data is to be stored. The RMFL
register (11 bits) is loaded with the maximum number of bytes
in the user fields plus 3 bytes ( +2 bytes for the FCS, +1 byte
because an interrupt will occur when the frame length is equal
to the length set by the number in the register) .