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參數(shù)資料
| 型號(hào)： | MTB52N06VL |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | JFETs |
| 英文描述： | TMOS POWER FET 52 AMPERES 60 VOLTS |
| 中文描述： | 52 A, 60 V, 0.025 ohm, N-CHANNEL, Si, POWER, MOSFET |
| 文件頁(yè)數(shù)： | 7/10頁(yè) |
| 文件大?。?/td> | 200K |
| 代理商： | MTB52N06VL |
7
Motorola TMOS Power MOSFET Transistor Device Data
INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must be
the correct size to ensure proper solder connection interface
between the board and the package. With the correct pad
geometry, the packages will self align when subjected to a
solder reflow process.
mm
inches
0.33
8.38
0.08
2.032
0.04
1.016
0.63
17.02
0.42
10.66
0.12
3.05
0.24
6.096
POWER DISSIPATION FOR A SURFACE MOUNT DEVICE
The power dissipation for a surface mount device is a
function of the drain pad size. These can vary from the
minimum pad size for soldering to a pad size given for
maximum power dissipation. Power dissipation for a surface
mount device is determined by TJ(max), the maximum rated
junction temperature of the die, R
θ
JA, the thermal resistance
from the device junction to ambient, and the operating
temperature, TA. Using the values provided on the data sheet,
PD can be calculated as follows:
PD =
TJ(max) – TA
R
θ
JA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature TA of 25
°
C, one can
calculate the power dissipation of the device. For a D2PAK
device, PD is calculated as follows.
PD =
175
°
C – 25
°
C
50
°
C/W
= 3.0 Watts
The 50
°
C/W for the D2PAK package assumes the use of the
recommended footprint on a glass epoxy printed circuit board
to achieve a power dissipation of 3.0 Watts. There are other
alternatives to achieving higher power dissipation from the
surface mount packages. One is to increase the area of the
drain pad. By increasing the area of the drain pad, the power
dissipation can be increased. Although one can almost double
the power dissipation with this method, one will be giving up
area on the printed circuit board which can defeat the purpose
of using surface mount technology. For example, a graph of
R
θ
JA versus drain pad area is shown in Figure 16.
Figure 16. Thermal Resistance versus Drain Pad
Area for the D2PAK Package (Typical)
2.5 Watts
A, AREA (SQUARE INCHES)
Board Material = 0.0625
″
G–10/FR–4, 2 oz Copper
TA = 25
°
C
60
70
50
40
30
20
16
14
12
10
8
6
4
2
0
3.5 Watts
5 Watts
T
°
R
θ
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| MTB52N06VLT4 | 制造商:ON Semiconductor 功能描述:Trans MOSFET N-CH 60V 52A 3-Pin(2+Tab) D2PAK T/R |
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