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參數(shù)資料
| 型號(hào)： | MTB75N06HD |
| 廠商： | MOTOROLA INC |
| 元件分類： | JFETs |
| 英文描述： | TMOS POWER FET 75 AMPERES 60 VOLTS |
| 中文描述： | 75 A, 60 V, 0.01 ohm, N-CHANNEL, Si, POWER, MOSFET |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 342K |
| 代理商： | MTB75N06HD |
1
Motorola TMOS Power MOSFET Transistor Device Data
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N–Channel Enhancement–Mode Silicon Gate
The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower RDS(on) capabilities. This advanced
high–cell density HDTMOS power FET is designed to withstand
high energy in the avalanche and commutation modes. This new
energy efficient design also offers a drain–to–source diode with a
fast recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
Avalanche Energy Specified
Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Short Heatsink Tab Manufactured — Not Sheared
Specially Designed Leadframe for Maximum Power Dissipation
Available in 24 mm 13–inch/800 Unit Tape & Reel, Add T4 Suffix to Part Number
MAXIMUM RATINGS
(TC = 25
°
C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–to–Source Voltage
VDSS
VDGR
VGS
VGSM
ID
ID
IDM
PD
60
Vdc
Drain–to–Gate Voltage (RGS = 1.0 M
)
Gate–to–Source Voltage — Continuous
Gate–to–Source Voltage
— Non–Repetitive (tp
≤
10 ms)
Drain Current — Continuous
Drain Current
— Continuous @ 100
°
C
Drain Current
— Single Pulse (tp
≤
10
μ
s)
Total Power Dissipation
Derate above 25
°
C
Total Power Dissipation @ TC = 25
°
C (1)
Operating and Storage Temperature Range
60
Vdc
±
20
±
30
Vdc
Vpk
75
50
225
Adc
Apk
125
1.0
2.5
Watts
W/
°
C
Watts
– 55 to 150
°
C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25
°
C
(VDD = 25 Vdc, VGS = 10 Vdc, IL = 75 Apk, L = 0.177 mH, RG = 25
)
Thermal Resistance — Junction to Case
Thermal Resistance
— Junction to Ambient
Thermal Resistance
— Junction to Ambient (1)
EAS
500
mJ
R
θ
JC
R
θ
JA
R
θ
JA
TL
1.0
62.5
50
°
C/W
Maximum Lead Temperature for Soldering Purposes, 1/8
″
from case for 10 seconds
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
260
°
C
Designer’s Data for “Worst Case” Conditions
— The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET, Designer’s and HDTMOS are trademarks of Motorola, Inc.
TMOS is a registered trademark of Motorola, Inc. Thermal Clad is a trademark of the Bergquist Company.
Preferred
devices are Motorola recommended choices for future use and best overall value.
REV 1
Order this document
by MTB75N06HD/D
SEMICONDUCTOR TECHNICAL DATA
D
S
G
TMOS POWER FET
75 AMPERES
60 VOLTS
RDS(on) = 10 mOHM
Motorola Preferred Device
CASE 418B–02, Style 2
D2PAK
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