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參數(shù)資料
| 型號(hào)： | MT92220 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 1023 Channel Voice Over IP/AAL2 Processor |
| 中文描述： | ATM NETWORK INTERFACE, PBGA608 |
| 封裝： | 31 X 31 MM, 2.50 MM HEIGHT, MS-034, EPBGA-608 |
| 文件頁(yè)數(shù)： | 30/210頁(yè) |
| 文件大?。?/td> | 1536K |
| 代理商： | MT92220 |
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Data Sheet
MT92220
30
Zarlink Semiconductor Inc.
5.0
This chapter describes the link-layer interfaces, as well as the packet reassembly structure used to transport their
data.
Link Layers
5.1
Interfaces
The MT92220 device can support 3 different types of primary link layers: Ethernet, which uses the MII bus to
communicate with an Ethernet PHY, ATM AAL5, which uses the UTOPIA bus, and Packet over SONET, which uses
a 16-bit POS-PHY bus to interface with a SONET PHY.
Each of these modes has its own headers to identify IP packets over the link layer and the MT92220 is directly
compatible to Physical Layer chips for each of the three interfaces.
In addition to its primary network interface, the MT92220 supports a secondary UTOPIA port that can be used to
connect a data SAR to the chip, or to daisy chain several MT92220 chips together. This secondary port is always a
UTOPIA port, independently of the configuration of the primary port. The chip is capable of treating IP packets from
both ports and can convert from one link layer to the other if need be.
5.2
Ethernet Interface
The MT92220, when configured to operate in Ethernet mode, can operate using 10 or 100 Mbps Ethernet in either
full- or half-duplex mode. When transmitting Ethernet packets, the chip will transmit the preamble, the packet itself
and the CRC-32 that it has calculated over the entire packet. The chip will abort its packet transfer in case of
collisions and it will back-off for a random period of time as specified by the Ethernet standard. If a packet
retransmission is attempted 16 consecutive times, the packet will be discarded and an error will be flagged to
registers.
When receiving Ethernet packets, the chip will verify the packet for the correct destination MAC address, the correct
payload size, the correct CRC-32. When parsing the packet, the chip will accept destination MAC addresses that
correspond to its own, as well as broadcast addresses; it can also be configured to accept all MAC addresses, as
well as selecting canonical or non-canonical formats of MAC addresses. The length/type is checked and the packet
is identified as IP/non-IP. The chip can also accept Ethernet headers that conform to the 802.1-p/Q specification.
Packets received on the Ethernet interface can range in size between 64 bytes and 1500 bytes plus headers, in
keeping with the Ethernet specification. Any larger or smaller packets will be discarded and an error bit will be
flagged in registers. The reporting of these errors is necessary for the support of Ethernet MIB.
All transmission and reception of data over Ethernet is done through the MII interface that communicates with an
Ethernet PHY.
5.3
Packet over SONET Interface
When using Packet over SONET, the MT92220 interfaces with a SONET PHY that allows packets to be transferred
over SONET using PPP. When using this mode, transmitted packets are given a 1 or 2 byte PPP header before
being sent onto the link: this header indicates that the packet is IP. When receiving packets, some filtering is done:
because PPP is, by definition, point-to-point, all packets received are indeed destined to the chip, but padding
packets must be deleted and non-IP packets must be flagged as such before being sent to the usual look-up flow.
The Packet over SONET interface uses a 16-bit POS-PHY bus used to communicate with SONET PHY. MT92220
doesn’t implement address bus therefore multi-PHY configuration is not supported.
The Packet over SONET interface can support packets ranging in size anywhere from 1 to 65535 bytes in length:
any packet longer than 64K bytes will be discarded and an error will be flagged in registers. The chip will also
discard any packets that are aborted by the PHY during transfer, as indicated by the
rxa_err
pin.
5.4
UTOPIA Interface
The MT92220 has a primary link layer port (Port A) that can be configured as Ethernet, ATM or Packet over
SONET. In addition, it has a secondary port (Port B) that is always configured to operate as an ATM port. Port B can
be used to interoperate with a secondary data SAR, or to daisy chain several MT92220 devices together onto a
single network connection. By keeping the same secondary port configuration independently of the mode in which
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT9300B | Multi-Channel Voice Echo Canceller |
| MT9300BL | Multi-Channel Voice Echo Canceller |
| MT9300BV | Multi-Channel Voice Echo Canceller |
| MT9315 | CMOS Acoustic Echo Canceller |
| MT933 | 3.3V 10/100 Fast Ethernet Transceiver to MII |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT92220BG | 制造商:Microsemi Corporation 功能描述: |
| MT9234MU | 功能描述:MODEM V.92 DATA/FAX USB WORLD RoHS:是 類別:計(jì)算機(jī)，辦公室 - 元件，配件 >> 調(diào)制解調(diào)器 系列:MultiMobile™ USB 標(biāo)準(zhǔn)包裝:1 系列:MultiModem® ZBA 數(shù)據(jù)格式:V.34，V.92 波特率:- 電源電壓:- 安裝類型:臺(tái)式 封裝/外殼:5.7" L x 4.3" W x 1.0" H（145mm x 109mm x 25mm） 供應(yīng)商設(shè)備封裝:- 包裝:散裝 |
| MT9234MU-CDC | 功能描述:MODEM V.92 DATA/FAX USB WORLD RoHS:是 類別:計(jì)算機(jī)，辦公室 - 元件，配件 >> 調(diào)制解調(diào)器 系列:MultiMobile™ USB 標(biāo)準(zhǔn)包裝:1 系列:MultiModem® ZBA 數(shù)據(jù)格式:V.34，V.92 波特率:- 電源電壓:- 安裝類型:臺(tái)式 封裝/外殼:5.7" L x 4.3" W x 1.0" H（145mm x 109mm x 25mm） 供應(yīng)商設(shè)備封裝:- 包裝:散裝 |
| MT9234MU-CDC-CP | 功能描述:MODEM V.92 DATA/FAX USB WORLD 25 RoHS:是 類別:計(jì)算機(jī)，辦公室 - 元件，配件 >> 調(diào)制解調(diào)器 系列:MultiMobile™ USB 標(biāo)準(zhǔn)包裝:1 系列:MultiModem® ZBA 數(shù)據(jù)格式:V.34，V.92 波特率:- 電源電壓:- 安裝類型:臺(tái)式 封裝/外殼:5.7" L x 4.3" W x 1.0" H（145mm x 109mm x 25mm） 供應(yīng)商設(shè)備封裝:- 包裝:散裝 |
| MT9234MU-CDC-XR | 功能描述:MODEM V.92 DATA/FAX USB WORLD RoHS:是 類別:計(jì)算機(jī)，辦公室 - 元件，配件 >> 調(diào)制解調(diào)器 系列:MultiMobile™ USB 標(biāo)準(zhǔn)包裝:1 系列:MultiModem® ZBA 數(shù)據(jù)格式:V.34，V.92 波特率:- 電源電壓:- 安裝類型:臺(tái)式 封裝/外殼:5.7" L x 4.3" W x 1.0" H（145mm x 109mm x 25mm） 供應(yīng)商設(shè)備封裝:- 包裝:散裝 |
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