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參數(shù)資料
| 型號(hào)： | MT92220 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 1023 Channel Voice Over IP/AAL2 Processor |
| 中文描述： | ATM NETWORK INTERFACE, PBGA608 |
| 封裝： | 31 X 31 MM, 2.50 MM HEIGHT, MS-034, EPBGA-608 |
| 文件頁數(shù)： | 16/210頁 |
| 文件大?。?/td> | 1536K |
| 代理商： | MT92220 |
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Data Sheet
MT92220
16
Zarlink Semiconductor Inc.
3.0
The CPU module serves as the main external interface of the MT92220 device. Through the CPU interface,
external agents can program the MT92220 registers, and read or write to the internal or external memories. The
interface is programmable to allow interaction with various types of external agents.
CPU interface
3.1
CPU Interface Description
The CPU interface is comprised of:
The CPU interface can be configured to operate in either Intel or Motorola mode, The MT92220 supports both 8-bit
or 16-bit data bus and multiplexed or non-multiplexed address/data pins.
Direct Access Select (DAS) as the MSB bit concatenated with a 15-bit address bus
16-bit data bus
2 interrupt signals
associated control signals.
Internally, a subset of registers -- CPU Interface Registers (000h to 00Ah), can be accessed with very low latency.
These registers contain address indirection and data indirection bits. The controlling CPU can choose to launch an
indirect access through these registers. Indirect reads will complete in due time when the data is available, while
indirect writes are performed almost instantaneously.
Direct accesses to the device can also be made. In these cases, accesses may take longer to complete. Any time a
direct access is done, the CPU interface will delay the access using the
cpu
_
rdy_ndtack
pin until the access has
completed internally. Note that direct writes are likely to complete very quickly as long as the write cache is not full.
3.2
CPU Interrupts
The CPU interface provides a programmable global interrupt capability. The interrupt signal are ‘interrupt1’and
‘interrupt2’, pins Y5 and W4 respectively. Both interrupts have programmability to select their active polarity
(open-collector drive) via registers ‘interrupt1_conf’and ‘interrupt2_conf’, addresses 214h and 216h respectively.
Interrupt1 provides the capability to program a minimum acceptable period between interrupts. The period is
programmed in us units via the ‘interrupt1_conf’ register. This provides a ‘frequency interrupt controller’ facility and
mask the assertion of further interrupts until the specified period of time has elapsed. The mask period will start
when the interrupt1_treated[15] bit in the register ‘interrupt_treated’ (address 212h) is set. When Interrupt2 is
enabled it is always activated when an interrupt condition occurs.
The operation of the CPU interrupt network is common for all modules. When an interrupt is asserted, an interrupt
flag is set to identify the module where the interrupt was generated. On completion of the ISR the interrupt must be
cleared as the interrupt will remain asserted until it is de-asserted by the user. All Interrupt Enable Registers have a
mirror Status Register. Hence, the bit positioning of the interrupt enables and the corresponding status bits are
identical.
Interrupt pins are always tri-stated when inactive.
3.2.1
Example Interrupt Flow
Upon the initialization of the Globe Interrupt pins the following methodology is adopted to identify the source of the
interrupt. For this example Interrupt2 is employed and the CPU module will be the source of the interruption.
3.2.1.1
Interrupt Initialization
Set interrupt polarity, register interrupt2_conf[15:14], address 216h.
Enable Inetrrupt2 for the CPU module by setting bit 0 in inetrrupt2_enble register (21Ch). The MT92220 will
generate an interrupt on interrupt2 pin according to the modules enabled in inetrrupt2_enable.
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