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參數(shù)資料
| 型號： | MT90823AP |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 路由/交換 |
| 英文描述： | 3V Large Digital Switch |
| 中文描述： | TELECOM, DIGITAL TIME SWITCH, PQCC84 |
| 封裝： | PLASTIC, MS-018AF, LCC-84 |
| 文件頁數(shù)： | 8/46頁 |
| 文件大?。?/td> | 663K |
| 代理商： | MT90823AP |
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MT90823
Data Sheet
8
Zarlink Semiconductor Inc.
Device Overview
The MT90823 Large Digital Switch is capable of switching up to 2,048
×
2,048 channels. The MT90823 is designed
to switch 64 kb/s PCM or N x 64 kb/s data. The device maintains frame integrity in data applications and minimum
throughput delay for voice applications on a per channel basis.
The serial input streams of the MT90823 can have a bit rate of 2.048, 4.096 or 8.192 Mbit/s and are arranged in
125
μ
s wide frames, which contain 32, 64 or 128 channels, respectively. The data rates on input and output
streams are identical.
By using Zarllink’s message mode capability, the microprocessor can access input and output time-slots on a per
channel basis. This feature is useful for transferring control and status information for external circuits or other ST-
BUS devices. The MT90823 automatically identifies the polarity of the frame synchronization input signal and
configures its serial streams to be compatible to either ST-BUS or GCI formats.
Two different microprocessor bus interfaces can be selected through the Input Mode pin (IM): Non-multiplexed or
Multiplexed. These interfaces provide compatibility with multiplexed and Motorola multiplexed/non-multiplexed
buses.
The frame offset calibration function allows users to measure the frame offset delay using a frame evaluation pin
(FE). The input offset delay can be programmed for individual streams using internal frame input offset registers,
see Table 11.
The internal loopback allows the ST-BUS output data to be looped around to the ST-BUS inputs for diagnostic
purposes.
76
57
54
B11
ODE
Output Drive Enable (5 V Tolerant Input):
This is the
output enable control for the STo0-15 serial outputs.
When ODE input is low and the OSB bit of the IMS
register is low, STo0-15 are in a high impedance state.
If this input is high, the STo0-15 output drivers are
enabled. However, each channel may still be put into a
high impedance state by using the per channel control
bit in the connection memory.
77 -
84
58-65
55 -
62
A11,B10,A10,B9,
A9,A8,B8,A7
STo0 - 7
Data Stream Output 0 to 7 (5 V Tolerant Three-state
Outputs):
Serial data Output stream. These streams
have selectable data rates of 2.048, 4.096 or
8.192 Mb/s.
-
1 - 4,
27 -
30,
51 -
54
77 -
80
1 - 2,
24 -
27,
49 -
52,
74 -
77,
99 -
100
NC
No connection.
Pin Description (continued)
Pin #
Name
Description
84
PLCC
100
MQFP
100
LQFP
120
BGA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90826 | Quad Digital Switch |
| MT90826AG | Quad Digital Switch |
| MT90826AL | Quad Digital Switch |
| MT90826AL1 | Quad Digital Switch |
| MT90826AV | Quad Digital Switch |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90823AP1 | 制造商:Microsemi Corporation 功能描述:LOW VOL LARGE DIGITAL SWCH |
| MT90826 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Quad Digital Switch |
| MT90826AG | 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 4K X 4K/2K X 2K/1K X 1K 3.3V 160BGA - Trays |
| MT90826AG2 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 4K X 4K/2K X 2K/1K X 1K 3.3V 160BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 4K X 4K/2K X 2K/1K X 1K 3.3V 160BGA - Trays |
| MT90826AL | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 4K X 4K/2K X 2K/1K X 1K 3.3V 160MQFP - Trays |
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