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參數(shù)資料
| 型號： | MT90823AP |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 路由/交換 |
| 英文描述： | 3V Large Digital Switch |
| 中文描述： | TELECOM, DIGITAL TIME SWITCH, PQCC84 |
| 封裝： | PLASTIC, MS-018AF, LCC-84 |
| 文件頁數(shù)： | 13/46頁 |
| 文件大?。?/td> | 663K |
| 代理商： | MT90823AP |
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MT90823
Data Sheet
13
Zarlink Semiconductor Inc.
Table 2 - Variable Throughput Delay Value
Table 3 - Constant Throughput Delay Value
For multiplexed operation, the 8-bit data and address (AD0-AD7), 8-bit Data (D8-D15), Address strobe/Address
latch enable (AS/ALE), Data strobe/Read (DS/RD), Read/Write /Write (R/W / WR), Chip select (CS) and Data
transfer acknowledge (DTA) signals are required. See Figure 13 and Figure 14 for multiplexed parallel microport
timing.
For the Motorola non-multiplexed bus, the 16-bit data bus (AD0-AD7, D8-D15), 8-bit address bus (A0-A7) and 4
control lines (CS, DS, R/W and DTA) signals are required. See Figure 15 for Motorola non- multiplexed microport
timing.
The MT90823 microport provides access to the internal registers, connection and data memories. All locations
provide read/write access except for the data memory and the frame alignment register which are read only.
Memory Mapping
The address bus on the microprocessor interface selects the MT90823 internal registers and memory. If the A7
address input is low, then the control (CR), interface mode selection (IMS), frame alignment (FAR) and frame input
offset (FOR) registers are addressed by A6 to A0 as shown in Table 4.
If the A7 address input is high, then the remaining address input lines are used to select up to 128 memory
subsection locations. The number selected corresponds to the maximum number of channels per input or output
stream. The address input lines and the stream address bits (STA) of the control register allow access to the entire
data and connection memories.
The control and IMS registers together control all the major functions of the device. The IMS register should be
programmed immediately after system power-up to establish the desired switching configuration (see “Serial Data
Interface Timing” and “Switching Configurations” ).
The control register controls switching operations in the MT90823. It selects the internal memory locations that
specify the input and output channels selected for switching.
Input Rate
Delay for Variable Throughput Delay Mode
(m - output channel number)
(n - input channel number))
m < n
m = n, n+1, n+2
m > n+2
2.048 Mb/s
32 - (n-m) time-slots
m-n + 32 time-slots
m-n time-slots
4.096 Mb/s
64 - (n-m) time-slots
m-n + 64 time-slots
m-n time-slots
8.192 Mb/s
128 - (n-m) time-slots
m-n + 128 time-slots
m-n time-slots
Input Rate
Delay for Constant Throughput Delay Mode
(m - output channel number)
(n - input channel number))
2.048 Mb/s
32 + (32 - n) + (m - 1) time-slots
4.096 Mb/s
64 + (64 - n) + (m- 1) time-slots
8.192 Mb/s
128 + (128 - n) + (m- 1) time-slots
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PDF描述 |
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| MT90826 | Quad Digital Switch |
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| MT90826AL | Quad Digital Switch |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90823AP1 | 制造商:Microsemi Corporation 功能描述:LOW VOL LARGE DIGITAL SWCH |
| MT90826 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Quad Digital Switch |
| MT90826AG | 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 4K X 4K/2K X 2K/1K X 1K 3.3V 160BGA - Trays |
| MT90826AG2 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 4K X 4K/2K X 2K/1K X 1K 3.3V 160BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 4K X 4K/2K X 2K/1K X 1K 3.3V 160BGA - Trays |
| MT90826AL | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 4K X 4K/2K X 2K/1K X 1K 3.3V 160MQFP - Trays |
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