參數(shù)資料
型號(hào): MT90823AP
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: 3V Large Digital Switch
中文描述: TELECOM, DIGITAL TIME SWITCH, PQCC84
封裝: PLASTIC, MS-018AF, LCC-84
文件頁數(shù): 18/46頁
文件大小: 663K
代理商: MT90823AP
MT90823
Data Sheet
18
Zarlink Semiconductor Inc.
Table 10 - Frame Alignment (FAR) Register Bits
Bit
Name
Description
15 - 13
Unused
Must be zero for normal operation.
12
CFE
Complete Frame Evaluation.
When CFE = 1, the frame evaluation is
completed and bits FD10 to FD0 bits contains a valid frame alignment offset.
This bit is reset to zero, when SFE bit in the IMS register is changed from 1 to
0.
11
FD11
Frame Delay Bit 11.
The falling edge of FE (or rising edge for GCI mode) is
sampled during the CLK-high phase (FD11 = 1) or during the CLK-low phase
(FD11 = 0). This bit allows the measurement resolution to 1/2 CLK cycle.
10 - 0
FD10-0
Frame Delay Bits.
The binary value expressed in these bits refers to the
measured input offset value. These bits are reset to zero when the SFE bit of
the IMS register changes from 1 to 0. (FD10 = MSB, FD0 = LSB)
Read Address:
Reset Value:
02
H
,
0000
H
.
7
6
5
4
3
2
1
0
8
9
10
11
12
13
FD0
FD1
FD2
FD3
FD4
FD5
FD6
FD7
FD8
FD9
FD10
FD11
CFE
0
0
0
14
15
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